✓ CI.checkpatch: success for Add support for 3 VDSC engines 12 slices (rev2)

[Patchwork]

== Series Details ==

Series: Add support for 3 VDSC engines 12 slices (rev2)
URL   : https://patchwork.freedesktop.org/series/139933/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 79acc50d4c6b3a8d9b75649a55926db8d4523eef
Author: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
Date:   Mon Oct 14 13:40:00 2024 +0530

    drm/i915/dp: Add support for 3 vdsc engines and 12 slices.
    
    Certain resolutions require 12 DSC slices support along with ultrajoiner.
    For such cases, the third VDSC Engine per Pipe is enabled. Each VDSC
    Engine processes 1 Slice, resulting in a total of 12 VDSC Instances
    (4 Pipes * 3 VDSC Instances per Pipe).
    Add support for 12 DSC slices and 3 VDSC engines for such modes.
    
    Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
+ /mt/dim checkpatch b3b6cc77bee51d59ae1b3d2e534b05d2a635dc90 drm-intel
65656903010a drm/i915/display: Prepare for dsc 3 stream splitter
e74fab005535 drm/i915/vdsc: Use VDSC0/VDSC1 for LEFT/RIGHT VDSC engine
1c552cf444f0 drm/i915/vdsc: Add register bits for VDSC2 engine
7b2be4fe41e6 drm/i915/vdsc: Add support for read/write PPS for DSC3
c3979c7ed8bc drm/i915/dp: Add check for hdisplay divisible by slice count
cedaabb4f412 drm/i915/display: Add DSC pixel replication
a09b729708f3 drm/i915/dp: Compute pixel replication count for DSC 12 slices case
3d4d4ff60deb drm/i915/dsc: Account for Odd pixel removal
79acc50d4c6b drm/i915/dp: Add support for 3 vdsc engines and 12 slices.