✓ CI.checkpatch: success for drm/i915/psr: Implement WA to help reach PC10 (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/psr: Implement WA to help reach PC10 (rev3)
URL   : https://patchwork.freedesktop.org/series/139512/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 8eea840b1cdde37acce59a186a651ba9845a8c90
Author: Suraj Kandpal <suraj.kandpal at intel.com>
Date:   Thu Oct 17 13:25:33 2024 +0530

    drm/i915/psr: Implement WA to help reach PC10
    
    To reach PC10 when PKG_C_LATENCY is configure we must do the following
    things
    1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
    2) Allow PSR2 deep sleep when DC5 can be entered
    3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
    eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
    not happening.
    
    --v2
    -Add debug prints
    
    --v3
    -use crtc as variable name for intel_crtc [Jani]
    -use encoder as variable name for intel_encoder [Jani]
    -No changes in intel_dp in compute_config_late [Jani]
    
    WA: 22019444797
    Signed-off-by: Suraj Kandpal <suraj.kandpal at intel.com>
+ /mt/dim checkpatch 6f9cc21188c822a692fbbcfaa7cb40cbd8082df0 drm-intel
8eea840b1cdd drm/i915/psr: Implement WA to help reach PC10