[PATCH 03/12] drm/i915/cx0: Extend C10 check to PTL

[Gustavo Sousa]

Quoting Matt Atwood (2024-10-18 17:49:32-03:00)
>From: Dnyaneshwar Bhadane <dnyaneshwar.bhadane at intel.com>
>
>When deciding the type of the phy, Add PTL support to make

s/Add/add/

>sure the correct path is taken for selection of C10 PHY.
>Only port A is connected C10 PHY for Pantherlake.
>
>Bspec:  72571
>Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane at intel.com>
>Signed-off-by: Matt Atwood <matthew.s.atwood at intel.com>
>---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c      | 9 +++++++--
> drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 +
> 2 files changed, 8 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>index 13a99f494680..73a151c81706 100644
>--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>@@ -34,6 +34,9 @@ bool intel_encoder_is_c10phy(struct intel_encoder *encoder)
>         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>         enum phy phy = intel_encoder_to_phy(encoder);
> 
>+        if (IS_PANTHERLAKE(i915) && phy == PHY_A)
>+                return true;
>+
>         if ((IS_LUNARLAKE(i915) || IS_METEORLAKE(i915)) && phy < PHY_C)
>                 return true;
> 
>@@ -221,7 +224,8 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
>          * down and let the message bus to end up
>          * in a known state
>          */
>-        intel_cx0_bus_reset(encoder, lane);
>+        if (DISPLAY_VER(i915) < 30)
>+                intel_cx0_bus_reset(encoder, lane);

I think skipping the call to intel_cx0_bus_reset() should be a patch on
its own.

With this patch containing only the change to intel_encoder_is_c10phy(),

    Reviewed-by: Gustavo Sousa <gustavo.sousa at intel.com>

--
Gustavo Sousa

> 
>         return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, val);
> }
>@@ -310,7 +314,8 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
>          * down and let the message bus to end up
>          * in a known state
>          */
>-        intel_cx0_bus_reset(encoder, lane);
>+        if (DISPLAY_VER(i915) < 30)
>+                intel_cx0_bus_reset(encoder, lane);
> 
>         return 0;
> }
>diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>index b7041b578e5e..bd8c3de57dcd 100644
>--- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>+++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>@@ -67,6 +67,7 @@ static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
> #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE)
> #define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE)
> #define IS_BATTLEMAGE(dev_priv)  IS_PLATFORM(dev_priv, XE_BATTLEMAGE)
>+#define IS_PANTHERLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_PANTHERLAKE)
> 
> #define IS_HASWELL_ULT(dev_priv) (dev_priv && 0)
> #define IS_BROADWELL_ULT(dev_priv) (dev_priv && 0)
>-- 
>2.45.0
>