[PATCH 06/16] drm/i915/dp: Ensure hactive is divisible by slice count

[Kandpal, Suraj]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal at intel.com>
> Sent: Wednesday, October 23, 2024 12:23 PM
> To: intel-gfx at lists.freedesktop.org
> Cc: intel-xe at lists.freedesktop.org; Kandpal, Suraj <suraj.kandpal at intel.com>
> Subject: [PATCH 06/16] drm/i915/dp: Ensure hactive is divisible by slice count
> 
> According to the DSC spec, the slice width should be chosen such that the
> picture width (hactive) is evenly divisible by the slice width.
> If not, extra pixels (padding) must be added to the last slice to ensure all slices
> have the same width.
> 
> Currently, we do not support handling these extra pixels.
> Therefore, select a slice count that evenly divides the hactive (slice_width =
> hactive / slice_count).
> 
> This check is already implemented for DSI, where the slice count is selected
> from the BIOS.
> 
> For DP, currently with 1, 2, 4 slices per pipe it is unlikely to have slice count not
> being able to divide hactive, but with 3 DSC engines and 3 slices, we can have
> such cases. Adding this check prepares for future scenarios where such
> configurations might be used.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal at intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 77487a55280c..3b20ea844925 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1037,6 +1037,9 @@ u8 intel_dp_dsc_get_slice_count(const struct
> intel_connector *connector,
>  		if (num_joined_pipes > 1 && valid_dsc_slicecount[i] < 2)
>  			continue;
> 
> +		if (mode_hdisplay % test_slice_count)
> +			continue;
> +
>  		if (min_slice_count <= test_slice_count)
>  			return test_slice_count;
>  	}
> --
> 2.45.2