✗ CI.checkpatch: warning for drm/xe/mmap: Add mmap support for PCI memory barrier (rev4)

[Patchwork]

== Series Details ==

Series: drm/xe/mmap: Add mmap support for PCI memory barrier (rev4)
URL   : https://patchwork.freedesktop.org/series/139769/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit fc52a08622b9d5b8fd121a1fa378e0d47d376e8c
Author: Tejas Upadhyay <tejas.upadhyay at intel.com>
Date:   Wed Oct 23 15:41:21 2024 +0530

    drm/xe/mmap: Add mmap support for PCI memory barrier
    
    In order to avoid having userspace to use MI_MEM_FENCE,
    we are adding a mechanism for userspace to generate a
    PCI memory barrier with low overhead (avoiding IOCTL call
    as well as writing to VRAM will adds some overhead).
    
    This is implemented by memory-mapping a page as uncached
    that is backed by MMIO on the dGPU and thus allowing userspace
    to do memory write to the page without invoking an IOCTL.
    We are selecting the MMIO so that it is not accessible from
    the PCI bus so that the MMIO writes themselves are ignored,
    but the PCI memory barrier will still take action as the MMIO
    filtering will happen after the memory barrier effect.
    
    When we detect special defined offset in mmap(), We are mapping
    4K page which contains the last of page of doorbell MMIO range
    to userspace for same purpose.
    
    For user to query special offset we are adding special flag in
    mmap_offset ioctl which needs to be passed as follows,
     struct drm_xe_gem_mmap_offset mmo = {
                    .handle = 0, /* this must be 0 */
                    .flags = DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER,
            };
     igt_ioctl(fd, DRM_IOCTL_XE_GEM_MMAP_OFFSET, &mmo);
     map = mmap(NULL, size, PROT_WRITE, MAP_SHARED, fd, mmo);
    
    Note: Test coverage for this is added by IGT
          https://patchwork.freedesktop.org/series/140368/  here.
    
    V4(MAuld)
      - Add kernel-doc for uapi change
      - Restrict page size to 4K
    V3(MAuld)
      - Remove offset defination from UAPI to be able to change later
      - Edit commit message for special flag addition
    V2(MAuld)
      - Add fault handler with dummy page to handle unplug device
      - Add Build check for special offset to be below normal start page
      - Test d3hot, mapping seems to be valid in d3hot as well
      - Add more info to commit message
    
    Cc: Matthew Auld <matthew.auld at intel.com>
    Cc: Michal Mrozek <michal.mrozek at intel.com>
    Signed-off-by: Tejas Upadhyay <tejas.upadhyay at intel.com>
+ /mt/dim checkpatch a2307a4a7aa44b9913e55a7d1dfdd53d98b19e92 drm-intel
fc52a08622b9 drm/xe/mmap: Add mmap support for PCI memory barrier
-:225: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#225: FILE: include/uapi/drm/xe_drm.h:826:
+ * ^I.handle = 0, (this must be set to 0)$

-:226: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#226: FILE: include/uapi/drm/xe_drm.h:827:
+ * ^I.flags = DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER,$

-:230: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line
#230: FILE: include/uapi/drm/xe_drm.h:831:
+ * map = mmap(NULL, size, PROT_WRITE, MAP_SHARED, fd, mmo);
+*/

total: 0 errors, 3 warnings, 0 checks, 165 lines checked