[PATCH v4 06/11] drm/i915/cx0: Remove bus reset after every c10 transaction

[Gustavo Sousa]

Quoting Clint Taylor (2024-10-24 19:31:09-03:00)
>C10 phy timeouts occur on xe3lpd if the c10 bus is reset every
>transaction. Starting with xe3lpd this is bus reset not necessary
>

Yeah. Resetting the bus on every transaction was never part of the Bspec
and it was added as a workaround for issues observed with MTL, right
Mika?

I wonder if we also see the issues with Xe2_LPD... If not, maybe we
could instead do the resets only for Xe_LPD+.

In any case, since the reset was not part of the BSpec and was causing
issues for Xe3_LPD:

Reviewed-by: Gustavo Sousa <gustavo.sousa at intel.com>

We might want extend the commit message to provide more context (i.e.
resets not required by the BSpec and were added as workaround for MTL).

--
Gustavo Sousa

>Signed-off-by: Clint Taylor <clinton.a.taylor at intel.com>
>---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>index 4d6e1c135bdc..c6e0cbff5201 100644
>--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>@@ -224,7 +224,8 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
>          * down and let the message bus to end up
>          * in a known state
>          */
>-        intel_cx0_bus_reset(encoder, lane);
>+        if (DISPLAY_VER(i915) < 30)
>+                intel_cx0_bus_reset(encoder, lane);
> 
>         return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, val);
> }
>@@ -313,7 +314,8 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
>          * down and let the message bus to end up
>          * in a known state
>          */
>-        intel_cx0_bus_reset(encoder, lane);
>+        if (DISPLAY_VER(i915) < 30)
>+                intel_cx0_bus_reset(encoder, lane);
> 
>         return 0;
> }
>-- 
>2.25.1
>