✓ CI.checkpatch: success for Add support for 3 VDSC engines 12 slices (rev6)

[Patchwork]

== Series Details ==

Series: Add support for 3 VDSC engines 12 slices (rev6)
URL   : https://patchwork.freedesktop.org/series/139933/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 2bbe6e6ea28d2a9c565ad6b36fa656e0311af1fe
Author: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
Date:   Sun Oct 27 19:15:57 2024 +0530

    drm/i915/dp: Enable 3 DSC engines for 12 slices
    
    Certain resolutions require 12 DSC slices support along with ultrajoiner.
    For such cases, the third DSC Engine per Pipe is enabled. Each DSC
    Engine processes 1 Slice, resulting in a total of 12 VDSC slices
    (4 Pipes * 3 DSC Instances per Pipe).
    Add support for 12 DSC slices and 3 DSC engines for such modes.
    
    v2: Add missing check for 3 slices support only with 4 joined pipes.
    (Suraj)
    
    Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
    Reviewed-by: Suraj Kandpal <suraj.kandpal at intel.com>
+ /mt/dim checkpatch 3ec61d11c7429a65dcc3ac46b9e845f13891a306 drm-intel
95bb3dbf56ca drm/i915/dp: Update Comment for Valid DSC Slices per Line
460d55687f4a drm/i915/display: Prepare for dsc 3 stream splitter
7479d270d760 drm/i915/vdsc: Use VDSC0/VDSC1 for LEFT/RIGHT VDSC engine
61ec849b5673 drm/i915/vdsc: Introduce 3rd VDSC engine VDSC2
db381e151383 drm/i915/vdsc: Add support for read/write PPS for 3rd DSC engine
35d73ca2d501 drm/i915/dp: Ensure hactive is divisible by slice count
2bbe6e6ea28d drm/i915/dp: Enable 3 DSC engines for 12 slices