✓ CI.checkpatch: success for Add support for 3 VDSC engines 12 slices (rev7)

[Patchwork]

== Series Details ==

Series: Add support for 3 VDSC engines 12 slices (rev7)
URL   : https://patchwork.freedesktop.org/series/139933/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 00b550e7845e6ee6d702d6f1f091532fea93da81
Author: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
Date:   Wed Oct 30 09:40:36 2024 +0530

    drm/i915/dp: Enable 3 DSC engines for 12 slices
    
    Certain resolutions require 12 DSC slices support along with ultrajoiner.
    For such cases, the third DSC Engine per Pipe is enabled. Each DSC
    Engine processes 1 Slice, resulting in a total of 12 VDSC slices
    (4 Pipes * 3 DSC Instances per Pipe).
    Add support for 12 DSC slices and 3 DSC engines for such modes.
    
    v2: Add missing check for 3 slices support only with 4 joined pipes.
    (Suraj)
    
    Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
    Reviewed-by: Suraj Kandpal <suraj.kandpal at intel.com>
+ /mt/dim checkpatch b97473387ce132222c9b71f7cf39c2cd814cbb6f drm-intel
fb9012132a5b drm/i915/dp: Update Comment for Valid DSC Slices per Line
93198008453a drm/i915/display: Prepare for dsc 3 stream splitter
e43b4e89f2cb drm/i915/vdsc: Use VDSC0/VDSC1 for LEFT/RIGHT VDSC engine
cbb8b16df943 drm/i915/vdsc: Introduce 3rd VDSC engine VDSC2
ce0969b91b97 drm/i915/vdsc: Add support for read/write PPS for 3rd DSC engine
3202e5aca2f1 drm/i915/dp: Ensure hactive is divisible by slice count
00b550e7845e drm/i915/dp: Enable 3 DSC engines for 12 slices