[PATCH v2 1/2] drm/xe: Set mask bits for CCS_MODE register

[Lucas De Marchi]

On Tue, Oct 08, 2024 at 11:34:59AM -0500, Lucas De Marchi wrote:
>On Tue, Oct 08, 2024 at 01:06:27PM +0530, Balasubramani Vivekanandan wrote:
>>CCS_MODE register requires setting mask bits from Xe2+ platforms. Set
>>the mask bits unconditionally, as those bits are unused for older
>>platforms.
>
>xe_gt_ccs_mode_enabled() doesn't agree with this statement and
>we do use PVC and DG2 for tests.

I actually misread what you wrote... I thought it was about not using
ccs_mode for older platforms. However this is about the old register
having unused bits in the upper part.

Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

thanks
Lucas De Marchi

>
>Lucas De Marchi
>
>>
>>Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan at intel.com>
>>---
>>drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +-
>>drivers/gpu/drm/xe/xe_gt_ccs_mode.c  | 6 ++++++
>>2 files changed, 7 insertions(+), 1 deletion(-)
>>
>>diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>index 9dd70934ca15..e136b663af98 100644
>>--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>@@ -562,7 +562,7 @@
>> *   [4-6]     RSVD
>> *   [7]       Disabled
>> */
>>-#define CCS_MODE				XE_REG(0x14804)
>>+#define CCS_MODE				XE_REG(0x14804, XE_REG_OPTION_MASKED)
>>#define   CCS_MODE_CSLICE_0_3_MASK		REG_GENMASK(11, 0) /* 3 bits per cslice */
>>#define   CCS_MODE_CSLICE_MASK			0x7 /* CCS0-3 + rsvd */
>>#define   CCS_MODE_CSLICE_WIDTH			ilog2(CCS_MODE_CSLICE_MASK + 1)
>>diff --git a/drivers/gpu/drm/xe/xe_gt_ccs_mode.c b/drivers/gpu/drm/xe/xe_gt_ccs_mode.c
>>index 9360ac4de489..246190b3e2bb 100644
>>--- a/drivers/gpu/drm/xe/xe_gt_ccs_mode.c
>>+++ b/drivers/gpu/drm/xe/xe_gt_ccs_mode.c
>>@@ -68,6 +68,12 @@ static void __xe_gt_apply_ccs_mode(struct xe_gt *gt, u32 num_engines)
>>		}
>>	}
>>
>>+	/*
>>+	 * Mask bits need to be set for the register. Though only Xe2+
>>+	 * platforms require setting of mask bits, it won't harm for older
>>+	 * platforms as these bits are unused there.
>>+	 */
>>+	mode |= CCS_MODE_CSLICE_0_3_MASK << 16;
>>	xe_mmio_write32(&gt->mmio, CCS_MODE, mode);
>>
>>	xe_gt_dbg(gt, "CCS_MODE=%x config:%08x, num_engines:%d, num_slices:%d\n",
>>-- 
>>2.34.1
>>