✓ CI.checkpatch: success for drm/xe/bmg: improve cache flushing behaviour

[Patchwork]

== Series Details ==

Series: drm/xe/bmg: improve cache flushing behaviour
URL   : https://patchwork.freedesktop.org/series/138102/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
9fe5037901cabbcdf27a6fe0dfb047ca1474d363
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 80c659a1eeb075865c7769d58ecf77116f988692
Author: Matthew Auld <matthew.auld at intel.com>
Date:   Mon Sep 2 16:37:45 2024 +0100

    drm/xe/bmg: improve cache flushing behaviour
    
    The BSpec seems to suggest that EN_L3_RW_CCS_CACHE_FLUSH must be toggled
    on for manual global invalidation to take effect and actually flush
    device cache, however this also turns on flushing for things like
    pipecontrol, which occurs between submissions for compute/render. This
    sounds like massive overkill for our needs, where we already have the
    manual flushing on the display side with the global invalidation. Some
    observations on BMG:
    
    1. Disabling l2 caching for host writes and stubbing out the driver
       global invalidation but keeping EN_L3_RW_CCS_CACHE_FLUSH enabled, has
       no impact on wb-transient-vs-display IGT, which makes sense since the
       pipecontrol is now flushing the device cache after the render copy.
       Without EN_L3_RW_CCS_CACHE_FLUSH the test then fails, which is also
       expected since device cache is now dirty and display engine can't see
       the writes.
    
    2. Disabling EN_L3_RW_CCS_CACHE_FLUSH, but keeping the driver global
       invalidation also has no impact on wb-transient-vs-display. This
       suggests that the global invalidation still works as expected and is
       flushing the device cache without EN_L3_RW_CCS_CACHE_FLUSH turned on.
    
    With that drop EN_L3_RW_CCS_CACHE_FLUSH.
    
    Signed-off-by: Matthew Auld <matthew.auld at intel.com>
    Cc: Matt Roper <matthew.d.roper at intel.com>
    Cc: Nirmoy Das <nirmoy.das at intel.com>
+ /mt/dim checkpatch f68a30b6b56c006ab1d6bca3b4ccf7aed1b2743e drm-intel
80c659a1eeb0 drm/xe/bmg: improve cache flushing behaviour