✓ CI.checkpatch: success for drm/xe/xe_gt_idle: add debugfs entry for powergating info (rev5)

[Patchwork]

== Series Details ==

Series: drm/xe/xe_gt_idle: add debugfs entry for powergating info (rev5)
URL   : https://patchwork.freedesktop.org/series/136477/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
c62d7e164862503a3662a095da1c6c9014248cb2
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 06627654d648d4b1a979c3e47c2cab0db49ff05e
Author: Riana Tauro <riana.tauro at intel.com>
Date:   Fri Sep 6 12:41:26 2024 +0530

    drm/xe/xe_gt_idle: add debugfs entry for powergating info
    
    Coarse Powergating is a power saving technique where Render and Media
    can be power-gated independently irrespective of the rest of the GT.
    
    For debug purposes, it is useful to expose the powergating information.
    
    v2: move to debugfs
        add details to commit message
        add per-slice status for media
        define reg bits in descending order (Matt Roper)
    
    v3: fix return statement
        fix kernel-doc
        use loop for media slices
        use helper function for status (Michal)
    
    v4: add pg prefix
        do not wake GT if in C6 (Badal)
    
    Signed-off-by: Riana Tauro <riana.tauro at intel.com>
    Reviewed-by: Badal Nilawar <badal.nilawar at intel.com>
    Acked-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
+ /mt/dim checkpatch e0cc4f231c70e2eaafe1ef83c5303fea926ea605 drm-intel
f00507515ebf drm/xe/xe_gt_idle: modify powergate enable condition
06627654d648 drm/xe/xe_gt_idle: add debugfs entry for powergating info