[PATCH 13/43] drm/xe/vram: Convert register access to use xe_mmio

[Lucas De Marchi]

On Tue, Sep 03, 2024 at 05:21:14PM GMT, Matt Roper wrote:
>Stop using GT pointers for register access.

could be more verbose in the commit message about the difference in
accessing MIRROR_FUSE3 (gt->mmio) vs GSMBASE (tile->mmio) since the
we are changing the behavior for the latter.

Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

Lucas De Marchi

>
>Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
>---
> drivers/gpu/drm/xe/xe_vram.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
>index 5bcd59190353..7e765b1499b1 100644
>--- a/drivers/gpu/drm/xe/xe_vram.c
>+++ b/drivers/gpu/drm/xe/xe_vram.c
>@@ -169,7 +169,7 @@ static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
> 		u64 offset_hi, offset_lo;
> 		u32 nodes, num_enabled;
>
>-		reg = xe_mmio_read32(gt, MIRROR_FUSE3);
>+		reg = xe_mmio_read32(&gt->mmio, MIRROR_FUSE3);
> 		nodes = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, reg);
> 		num_enabled = hweight32(nodes); /* Number of enabled l3 nodes */
>
>@@ -184,7 +184,8 @@ static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
> 		offset *= num_enabled; /* convert to SW view */
>
> 		/* We don't expect any holes */
>-		xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(gt, GSMBASE) - ccs_size),
>+		xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(&gt_to_tile(gt)->mmio, GSMBASE) -
>+					     ccs_size),
> 			      "Hole between CCS and GSM.\n");
> 	} else {
> 		reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
>@@ -256,7 +257,7 @@ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,
> 	if (xe->info.has_flat_ccs) {
> 		offset = get_flat_ccs_offset(gt, *tile_size);
> 	} else {
>-		offset = xe_mmio_read64_2x32(gt, GSMBASE);
>+		offset = xe_mmio_read64_2x32(&tile->mmio, GSMBASE);
> 	}
>
> 	/* remove the tile offset so we have just the available size */
>-- 
>2.45.2
>