[PATCH 5/9] drm/xe/xe3: Extend wa_15015404425 for xe3
Matt Atwood
matthew.s.atwood at intel.com
Fri Sep 6 21:51:49 UTC 2024
From: Tejas Upadhyay <tejas.upadhyay at intel.com>
wa_15015404425 applies to xe3 A0 step as well.
V2:
- make condition check simple(guludo)
Signed-off-by: Tejas Upadhyay <tejas.upadhyay at intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood at intel.com>
---
drivers/gpu/drm/xe/xe_mmio.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 3fd462fda625..4c3f07d89622 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -184,12 +184,12 @@ static void mmio_flush_pending_writes(struct xe_gt *gt)
struct xe_tile *tile = gt_to_tile(gt);
int i;
- if (tile->xe->info.platform != XE_LUNARLAKE)
- return;
-
- /* 4 dummy writes */
- for (i = 0; i < 4; i++)
- writel(0, tile->mmio.regs + DUMMY_REG_OFFSET);
+ if (tile->xe->info.platform == XE_LUNARLAKE ||
+ (tile->xe->info.platform == XE_PANTHERLAKE &&
+ tile->xe->info.step.graphics == STEP_A0))
+ /* 4 dummy writes */
+ for (i = 0; i < 4; i++)
+ writel(0, tile->mmio.regs + DUMMY_REG_OFFSET);
}
u8 xe_mmio_read8(struct xe_gt *gt, struct xe_reg reg)
--
2.44.0
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