[PATCH 2/9] drm/xe/xe3: Define Xe3 feature flags

[Matt Roper]

On Fri, Sep 06, 2024 at 02:51:46PM -0700, Matt Atwood wrote:
> From: Haridhar Kalvala <haridhar.kalvala at intel.com>
> 
> Define a common set of Xe3 feature flags
> and definitions that will be used for all
> platforms in this family.

Nitpick:  this commit message seems to be using very cramped line
wrapping for some reason.

> 
> The feature flags are inherited unchanged from
> Xe2 (XE2_FEATURES) platform.
> 
> Following B-spec details inherited from Xe2 feature
> flag definition commit.
> 
> Bspec: 58695
>  - dma_mask_size remains 46   (not documented in bspec)
>  - supports_usm=1             (Bspec 59651)
>  - has_flatccs=1              (Bspec 58797)
>  - has_4tile=1                (Bspec 58788)
>  - has_asid=1                 (Bspec 59654, 59265, 60288)
>  - has_range_tlb_invalidate=1 (Bspec 71126)
>  - five-level page table      (Bspec 59505)
>  - 1 VD + 1 VE + 1 SFC        (Bspec 67103, 70819)
>  - platform engine mask       (Bspec 60149)
> 
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Signed-off-by: Haridhar Kalvala <haridhar.kalvala at intel.com>
> Signed-off-by: Matt Atwood <matthew.s.atwood at intel.com>
> ---
>  drivers/gpu/drm/xe/xe_pci.c | 24 +++++++++++++++++++++++-
>  1 file changed, 23 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index c05ca61787be..b30d09508a38 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -180,6 +180,25 @@ static const struct xe_graphics_desc graphics_xe2 = {
>  	XE2_GFX_FEATURES,
>  };
>  
> +#define XE3_GFX_FEATURES \
> +	.dma_mask_size = 46, \
> +	.has_asid = true, \

The convention we've been using elsewhere is to use '1' instead of
'true' for these 1-bit fields.  We should probably be consistent here.

> +	.has_atomic_enable_pte_bit = 1, \
> +	.has_flat_ccs = true, \
> +	.has_range_tlb_invalidation = true, \
> +	.has_usm = true, \

Ditto on these two.

> +	.va_bits = 48, \
> +	.vm_max_level = 4, \
> +	.hw_engine_mask = \
> +		BIT(XE_HW_ENGINE_RCS0) | \
> +		BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \
> +		GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0)

I think we should have "has_indirect_ring_state = 1" included as well.

> +
> +static const struct xe_graphics_desc graphics_xe3 = {
> +	.name = "Xe3_LPG",
> +	XE3_GFX_FEATURES,
> +};

It doesn't look like there's actually any (intended) difference between
the Xe2 and Xe3 graphics feature flags for now.  Can't we just re-use
the graphics_xe2 structure (and XE2_GFX_FEATURES) until/unless a new
feature shows up that requires distinct handling?  That's already what
we're doing in this same patch for media down below...


Matt

> +
>  static const struct xe_media_desc media_xem = {
>  	.name = "Xe_M",
>  	.ver = 12,
> @@ -209,7 +228,7 @@ static const struct xe_media_desc media_xelpmp = {
>  };
>  
>  static const struct xe_media_desc media_xe2 = {
> -	.name = "Xe2_LPM / Xe2_HPM",
> +	.name = "Xe2_LPM / Xe2_HPM / Xe3_LPM",
>  	.hw_engine_mask =
>  		GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
>  		GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) |
> @@ -361,6 +380,8 @@ static const struct gmdid_map graphics_ip_map[] = {
>  	{ 1274, &graphics_xelpg },	/* Xe_LPG+ */
>  	{ 2001, &graphics_xe2 },
>  	{ 2004, &graphics_xe2 },
> +	{ 3000, &graphics_xe3 },
> +	{ 3001, &graphics_xe3 },
>  };
>  
>  /* Map of GMD_ID values to media IP */
> @@ -368,6 +389,7 @@ static const struct gmdid_map media_ip_map[] = {
>  	{ 1300, &media_xelpmp },
>  	{ 1301, &media_xe2 },
>  	{ 2000, &media_xe2 },
> +	{ 3000, &media_xe2 },
>  };
>  
>  #define INTEL_VGA_DEVICE(id, info) {			\
> -- 
> 2.44.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation