✗ CI.checkpatch: warning for drm/i915/cx0: Use one lane to set power state to ready in DP alt mode

[Patchwork]

== Series Details ==

Series: drm/i915/cx0: Use one lane to set power state to ready in DP alt mode
URL   : https://patchwork.freedesktop.org/series/138412/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
c62d7e164862503a3662a095da1c6c9014248cb2
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit c7d68bf966d9b1dafef86c384b5f2a8277f7e3a9
Author: Vamsi Krishna Brahmajosyula <vamsikrishna.brahmajosyula at gmail.com>
Date:   Fri Sep 6 23:16:01 2024 +0530

    drm/i915/cx0: Use one lane to set power state to ready in DP alt mode
    
    In DP alt mode one lane is owned by display and the other by usb
    intel_cx0pll_enable currently performs a power cycle ready on both
    the lanes in all cases.
    
    Address the todo to perfom power state ready only on the display lane
    when DP alt mode is enabled.
    
    Tested on Meteor Lake-P [Intel Arc Graphics] with DP alt mode.
    
    Signed-off-by: Vamsi Krishna Brahmajosyula <vamsikrishna.brahmajosyula at gmail.com>
+ /mt/dim checkpatch 36d222030253864ce07e73f27f631db5112d32c6 drm-intel
c7d68bf966d9 drm/i915/cx0: Use one lane to set power state to ready in DP alt mode
-:32: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#32: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2956:
+		intel_cx0_powerdown_change_sequence(encoder, maxpclk_lane,
+					    CX0_P2_STATE_READY);

-:35: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#35: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2959:
+		intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
 					    CX0_P2_STATE_READY);

total: 0 errors, 0 warnings, 2 checks, 15 lines checked