[PATCH] drm/xe/oa: Insert wmb/sfence before enabling OA

[Jani Nikula]

On Mon, 09 Sep 2024, Ashutosh Dixit <ashutosh.dixit at intel.com> wrote:
> We are occasionally seeing that OA Buffer register is not programmed (has
> value 0) when OA is enabled. This means OA has been enabled before it has
> been fully configured. Or, the register write enabling OA has overtaken
> previous OA configuration register writes.
>
> Therefore, insert a wmb/sfence to preserve OA register write ordering
> before enabling OA.
>
> v2: s/wmb()/xe_device_wmb()/
>
> Fixes: e936f885f1e9 ("drm/xe/oa/uapi: Expose OA stream fd")
> Reported-by: Guy Zadicario <guy.zadicario at intel.com>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit at intel.com>
> Cc: stable at vger.kernel.org

Please do not resend patches just to tweak something in the commit
message. It can be fixed while applying. Or when you have to make
another version with actual functional changes.

Please appreciate that this uses a full CI test run. It's not an
unlimited resource.

BR,
Jani.


> ---
>  drivers/gpu/drm/xe/xe_oa.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
> index 63286ed8457fa..4fb7aae37a94f 100644
> --- a/drivers/gpu/drm/xe/xe_oa.c
> +++ b/drivers/gpu/drm/xe/xe_oa.c
> @@ -440,6 +440,9 @@ static void xe_oa_enable(struct xe_oa_stream *stream)
>  	val = __format_to_oactrl(format, regs->oa_ctrl_counter_select_mask) |
>  		__oa_ccs_select(stream) | OAG_OACONTROL_OA_COUNTER_ENABLE;
>  
> +	/* Flush previous writes to HW before enabling OA */
> +	xe_device_wmb(stream->oa->xe);
> +
>  	xe_mmio_write32(stream->gt, regs->oa_ctrl, val);
>  }

-- 
Jani Nikula, Intel