[PATCH 5/9] drm/xe/xe3: Extend wa_15015404425 for xe3

[Matt Roper]

On Fri, Sep 06, 2024 at 04:52:39PM -0700, Matt Roper wrote:
> On Fri, Sep 06, 2024 at 02:51:49PM -0700, Matt Atwood wrote:
> > From: Tejas Upadhyay <tejas.upadhyay at intel.com>
> > 
> > wa_15015404425 applies to xe3 A0 step as well.
> 
> The workaround database can be a bit confusing for this one because the
> workaround is technically a platform / SoC workaround rather than a
> graphics workaround so it doesn't show up in the normal manner in the
> regular database we look at.  But that means this is "PTL A0" (the
> platform) not "Xe3 A0" (the GPU).   And that also means...
> 
> > 
> > V2:
> >   - make condition check simple(guludo)
> > 
> > Signed-off-by: Tejas Upadhyay <tejas.upadhyay at intel.com>
> > Signed-off-by: Matt Atwood <matthew.s.atwood at intel.com>
> > ---
> >  drivers/gpu/drm/xe/xe_mmio.c | 12 ++++++------
> >  1 file changed, 6 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> > index 3fd462fda625..4c3f07d89622 100644
> > --- a/drivers/gpu/drm/xe/xe_mmio.c
> > +++ b/drivers/gpu/drm/xe/xe_mmio.c
> > @@ -184,12 +184,12 @@ static void mmio_flush_pending_writes(struct xe_gt *gt)
> >  	struct xe_tile *tile = gt_to_tile(gt);
> >  	int i;
> >  
> > -	if (tile->xe->info.platform != XE_LUNARLAKE)
> > -		return;
> > -
> > -	/* 4 dummy writes */
> > -	for (i = 0; i < 4; i++)
> > -		writel(0, tile->mmio.regs + DUMMY_REG_OFFSET);
> > +	if (tile->xe->info.platform == XE_LUNARLAKE ||
> > +	    (tile->xe->info.platform == XE_PANTHERLAKE &&
> > +	     tile->xe->info.step.graphics == STEP_A0))
> 
> ...that the graphics stepping isn't really what we should be checking
> here either.  While it's likely true that A0 graphics are paired with A0
> SoC, we can't say for certain that, for example, A1 graphics won't also
> be paired with A0 SoC or that A0 graphics won't be paired with A1 SoC,
> etc.
> 
> To handle this properly, this is one of the cases where we really should
> be looking at the PCI revid to infer an SoC stepping rather than the
> GMD_ID's graphics stepping.

I also just noticed that this commit is broken since XE_PANTHERLAKE
isn't defined yet.


Matt

> 
> 
> Matt
> 
> > +		/* 4 dummy writes */
> > +		for (i = 0; i < 4; i++)
> > +			writel(0, tile->mmio.regs + DUMMY_REG_OFFSET);
> >  }
> >  
> >  u8 xe_mmio_read8(struct xe_gt *gt, struct xe_reg reg)
> > -- 
> > 2.44.0
> > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation