[PATCH v2] drm/xe/vram: fix ccs offset calculation

[Andi Shyti]

Hi Matt,

On Fri, Sep 13, 2024 at 01:00:24PM GMT, Matthew Auld wrote:
> Spec says SW is expected to round up to the nearest 128K, if not already
> aligned for the CC unit view of CCS. We are seeing the assert sometimes
> pop on BMG to tell us that there is a hole between GSM and CCS, as well
> as popping other asserts with having a vram size with strange alignment,
> which is likely caused by misaligned offset here.
> 
> BSpec: 68023
> Fixes: b5c2ca0372dc ("drm/xe/xe2hpg: Determine flat ccs offset for vram")
> Signed-off-by: Matthew Auld <matthew.auld at intel.com>
> Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray at intel.com>
> Cc: Akshata Jahagirdar <akshata.jahagirdar at intel.com>
> Cc: Shuicheng Lin <shuicheng.lin at intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Cc: <stable at vger.kernel.org> # v6.10+
> ---

and... what is the difference between v1 and v2? :-)

Andi

>  drivers/gpu/drm/xe/xe_vram.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
> index 7e765b1499b1..8e65cb4cc477 100644
> --- a/drivers/gpu/drm/xe/xe_vram.c
> +++ b/drivers/gpu/drm/xe/xe_vram.c
> @@ -181,6 +181,7 @@ static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
>  
>  		offset = offset_hi << 32; /* HW view bits 39:32 */
>  		offset |= offset_lo << 6; /* HW view bits 31:6 */
> +		offset = round_up(offset, SZ_128K); /* SW must round up to nearest 128K */
>  		offset *= num_enabled; /* convert to SW view */
>  
>  		/* We don't expect any holes */
> -- 
> 2.46.0
>