[PATCH v5 4/5] drm/xe: memirq infra changes for MSI-X

[Michal Wajdeczko]

On 17.09.2024 13:23, Ilia Levi wrote:
> From: Ilia Levi <ilia.levi at intel.com>
> 
> When using MSI-X, hw engines report interrupt status and source to engine
> instance 0. For this scenario, in order to differentiate between the
> engines, we need to pass different status/source pointers in the LRC.
> 
> The requirements on those pointers are:
> - Interrupt status should be 4KiB aligned
> - Interrupt source should be 64 bytes aligned
> 
> To accommodate this, we duplicate the current memirq page layout -
> allocating a page for each engine instance and pass this page in the LRC.
> Note that the same page can be reused for different engine types.
> For example, an LRC executing on CCS #x will have pointers to page #x,
> and an LRC executing on BCS #x will have the same pointers. Thus, to
> locate the proper page, the pointer accessors were modified to receive
> the hw engine.
> 
> Signed-off-by: Ilia Levi <ilia.levi at intel.com>

Reviewed-by: Michal Wajdeczko <michal.wajdeczko at intel.com>