[PATCH] drm/xe/xe2: Extend performance tuning to media GT

[Gustavo Sousa]

Quoting Gustavo Sousa (2024-09-18 11:21:20-03:00)
>Quoting Matt Roper (2024-09-17 19:42:43-03:00)
>>On Tue, Sep 17, 2024 at 02:02:38PM -0300, Gustavo Sousa wrote:
>>> Quoting Gustavo Sousa (2024-09-17 13:53:54-03:00)
>>> >With exception of "Tuning: L3 cache - media", we are currently applying
>>> >recommended performance tuning settings only for the primary GT. Let's
>>> >also apply them to the media GT when applicable.
>>> >
>>> >According to our spec, media GT registers CCCHKNREG1 and L3SQCREG* exist
>>> >only in Xe2_LPM and their offsets do not match their primary GT
>>> >counterparts. As such, we need to have Xe2_LPM-specific definitions for
>>> >them and apply the setting only for that specific IP.
>>> >
>>> >Both Xe2_HPM and Xe2_LPM contain STATELESS_COMPRESSION_CTRL and the
>>> >offset on the media GT matches the one on the primary one, so we can use
>>> >the common definition and apply the setting to both IPs.
>>> >
>>> >Bspec: 72161
>>> >Signed-off-by: Gustavo Sousa <gustavo.sousa at intel.com>
>>> >---
>>> > drivers/gpu/drm/xe/regs/xe_gt_regs.h |  6 ++++++
>>> > drivers/gpu/drm/xe/xe_tuning.c       | 19 +++++++++++++++++++
>>> > 2 files changed, 25 insertions(+)
>>> >
>>> >diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>> >index cf21de3adca6..2e655291a84a 100644
>>> >--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>> >+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>> >@@ -169,6 +169,8 @@
>>> > #define XEHP_SLICE_COMMON_ECO_CHICKEN1                XE_REG_MCR(0x731c, XE_REG_OPTION_MASKED)
>>> > #define   MSC_MSAA_REODER_BUF_BYPASS_DISABLE        REG_BIT(14)
>>> > 
>>> >+#define XE2LPM_CCCHKNREG1                        XE_REG_MCR(0x82a8)
>>
>>It looks like they forgot to fill in the complete row of bspec page
>>71186, but I don't believe this is in an MCR range on the media GT (and
>>we're not considering it an MCR range in xe_gt_mcr.c, so defining it as
>>such here will cause a mismatch --- looks like CI already flagged that).
>
>Yeah.
>
>Although this is also my bad on simply copy/pasting from the original
>definition and forgetting to check the steering table!
>
>And looks like we will also need a non-MCR definition for Xe2_HPM's
>STATELESS_COMPRESSION_CTRL.
>
>I'll revise the definitions of registers involved in this patch, thanks!

V2 of the this patch was sent with
https://patchwork.freedesktop.org/series/138844/.

--
Gustavo Sousa