[PATCH 2/3] drm/xe/xe2: Assume tuning settings also apply for future media GT

[Upadhyay, Tejas]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces at lists.freedesktop.org> On Behalf Of Gustavo
> Sousa
> Sent: Thursday, September 19, 2024 2:18 AM
> To: intel-xe at lists.freedesktop.org
> Cc: Roper, Matthew D <matthew.d.roper at intel.com>
> Subject: [PATCH 2/3] drm/xe/xe2: Assume tuning settings also apply for future
> media GT
> 
> We already make the assumption that recommended tuning settings for
> primary GT on Xe2 will also apply for future releases. Let's make the same
> assumption for the media GT. We can come back and define closed ranges
> when that becomes necessary.
> 
> Bspec: 72161
> Signed-off-by: Gustavo Sousa <gustavo.sousa at intel.com>
> ---
>  drivers/gpu/drm/xe/xe_tuning.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
> index 7a5b852af8d7..f62622f0be85 100644
> --- a/drivers/gpu/drm/xe/xe_tuning.c
> +++ b/drivers/gpu/drm/xe/xe_tuning.c
> @@ -33,7 +33,7 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
> 
> REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
>  	},
>  	{ XE_RTP_NAME("Tuning: L3 cache - media"),
> -	  XE_RTP_RULES(MEDIA_VERSION(2000)),
> +	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000,
> +XE_RTP_END_VERSION_UNDEFINED)),
>  	  XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5,
> L3_PWM_TIMER_INIT_VAL_MASK,
> 
> REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
>  	},
> @@ -43,7 +43,7 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>  			 SET(CCCHKNREG1, L3CMPCTRL))
>  	},
>  	{ XE_RTP_NAME("Tuning: Compression Overfetch - media"),
> -	  XE_RTP_RULES(MEDIA_VERSION(2000)),
> +	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000,
> +XE_RTP_END_VERSION_UNDEFINED)),
>  	  XE_RTP_ACTIONS(CLR(XE2LPM_CCCHKNREG1, ENCOMPPERFFIX),
>  			 SET(XE2LPM_CCCHKNREG1, L3CMPCTRL))
>  	},
> @@ -52,7 +52,7 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>  	  XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN))
>  	},
>  	{ XE_RTP_NAME("Tuning: Enable compressible partial write overfetch
> in L3 - media"),
> -	  XE_RTP_RULES(MEDIA_VERSION(2000)),
> +	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000,
> +XE_RTP_END_VERSION_UNDEFINED)),
>  	  XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG3,
> COMPPWOVERFETCHEN))
>  	},
>  	{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"), @@ -
> 61,7 +61,7 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>  			     COMPMEMRD256BOVRFETCHEN))
>  	},
>  	{ XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only - media"),
> -	  XE_RTP_RULES(MEDIA_VERSION(2000)),
> +	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000,
> +XE_RTP_END_VERSION_UNDEFINED)),
>  	  XE_RTP_ACTIONS(SET(XE2LPM_L3SQCREG2,
>  			     COMPMEMRD256BOVRFETCHEN))
>  	},
> @@ -71,7 +71,7 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
> 
> REG_FIELD_PREP(UNIFIED_COMPRESSION_FORMAT, 0)))
>  	},
>  	{ XE_RTP_NAME("Tuning: Stateless compression control - media"),
> -	  XE_RTP_RULES(MEDIA_VERSION(2000)),
> +	  XE_RTP_RULES(MEDIA_VERSION_RANGE(2000,
> +XE_RTP_END_VERSION_UNDEFINED)),
>  	  XE_RTP_ACTIONS(FIELD_SET(STATELESS_COMPRESSION_CTRL,
> UNIFIED_COMPRESSION_FORMAT,

Looks fine, 
Reviewed-by: Tejas Upadhyay <tejas.upadhyay at intel.com>

> 
> REG_FIELD_PREP(UNIFIED_COMPRESSION_FORMAT, 0)))
>  	},
> --
> 2.46.1