[PATCH v2 4/4] drm/xe/xe2: Add performance tuning for L3 cache flushing

[Gustavo Sousa]

Quoting Matt Roper (2024-09-20 16:26:44-03:00)
>On Fri, Sep 20, 2024 at 02:12:11PM -0300, Gustavo Sousa wrote:
>> A recommended performance tuning for LNL related to L3 cache flushing
>> was recently introduced in Bspec. Implement it.
>> 
>> v2:
>>   - Fix reference to Bspec. (Sai Teja, Tejas)
>>   - Use correct register name for "Tuning: L3 RW flush all Cache". (Sai
>>     Teja)
>>   - Use SCRATCH3_LBCF (with the underscore) for better readability.
>> 
>> Bspec: 72161
>> Cc: Sai Teja Pottumuttu <sai.teja.pottumuttu at intel.com>
>> Cc: Tejas Upadhyay <tejas.upadhyay at intel.com>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa at intel.com>
>> ---
>>  drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +++++
>>  drivers/gpu/drm/xe/xe_tuning.c       | 8 ++++++++
>>  2 files changed, 13 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> index 07315eb72eff..8d8f6a113a86 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> @@ -388,6 +388,9 @@
>>  #define L3SQCREG3                                XE_REG_MCR(0xb108)
>>  #define   COMPPWOVERFETCHEN                        REG_BIT(28)
>>  
>> +#define SCRATCH3_LBCF                                XE_REG_MCR(0xb154)
>> +#define   RWFLUSHALLEN                                REG_BIT(17)
>> +
>>  #define XEHP_L3SQCREG5                                XE_REG_MCR(0xb158)
>>  #define   L3_PWM_TIMER_INIT_VAL_MASK                REG_GENMASK(9, 0)
>>  
>> @@ -405,6 +408,8 @@
>>  
>>  #define XE2LPM_L3SQCREG3                        XE_REG_MCR(0xb608)
>>  
>> +#define XE2LPM_SCRATCH3_LBCF                        XE_REG_MCR(0xb654)
>> +
>>  #define XE2LPM_L3SQCREG5                        XE_REG_MCR(0xb658)
>>  
>>  #define XE2_TDF_CTRL                                XE_REG(0xb418)
>> diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
>> index 230369f108ab..39f50b6f94ce 100644
>> --- a/drivers/gpu/drm/xe/xe_tuning.c
>> +++ b/drivers/gpu/drm/xe/xe_tuning.c
>> @@ -75,6 +75,14 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>>            XE_RTP_ACTIONS(FIELD_SET(STATELESS_COMPRESSION_CTRL, UNIFIED_COMPRESSION_FORMAT,
>>                                     REG_FIELD_PREP(UNIFIED_COMPRESSION_FORMAT, 0)))
>>          },
>> +        { XE_RTP_NAME("Tuning: L3 RW flush all Cache"),
>> +          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2004, XE_RTP_END_VERSION_UNDEFINED)),
>
>The bspec tagging on this one is a bit of a mess right now, but when I
>look at the ticket that originally added this to the bspec, there's an
>underlined comment there that says "only for LNL."  We might want to
>check with the hardware guys to clarify if that's still the case and, if
>so, make this one of the special cases where the tuning applies solely
>to this one version.

Okay. I raised a question on the original ticket.

We might as well make this LNL-specific and then come back and use an
open range in necessary when we get more info. Thoughts?

--
Gustavo Sousa

>
>
>Matt
>
>> +          XE_RTP_ACTIONS(SET(SCRATCH3_LBCF, RWFLUSHALLEN))
>> +        },
>> +        { XE_RTP_NAME("Tuning: L3 RW flush all cache - media"),
>> +          XE_RTP_RULES(MEDIA_VERSION_RANGE(2000, XE_RTP_END_VERSION_UNDEFINED)),
>> +          XE_RTP_ACTIONS(SET(XE2LPM_SCRATCH3_LBCF, RWFLUSHALLEN))
>> +        },
>>  
>>          {}
>>  };
>> -- 
>> 2.46.1
>> 
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation