✓ CI.checkpatch: success for Xe2 performance tuning updates (rev3)

[Patchwork]

== Series Details ==

Series: Xe2 performance tuning updates (rev3)
URL   : https://patchwork.freedesktop.org/series/138844/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 249f723c65bd28508fe11c48979fd52f16309bb4
Author: Gustavo Sousa <gustavo.sousa at intel.com>
Date:   Fri Sep 20 18:13:18 2024 -0300

    drm/xe/xe2: Add performance tuning for L3 cache flushing
    
    A recommended performance tuning for LNL related to L3 cache flushing
    was recently introduced in Bspec. Implement it.
    
    Unlike the other existing tuning settings, we limit this one for LNL
    only, since there is no info about whether this would be applicable to
    other platforms yet. In the future we can come back and use IP version
    ranges if applicable.
    
    v2:
      - Fix reference to Bspec. (Sai Teja, Tejas)
      - Use correct register name for "Tuning: L3 RW flush all Cache". (Sai
        Teja)
      - Use SCRATCH3_LBCF (with the underscore) for better readability.
    v3:
      - Limit setting to LNL only. (Matt)
    
    Bspec: 72161
    Cc: Sai Teja Pottumuttu <sai.teja.pottumuttu at intel.com>
    Cc: Tejas Upadhyay <tejas.upadhyay at intel.com>
    Cc: Matt Roper <matthew.d.roper at intel.com>
    Signed-off-by: Gustavo Sousa <gustavo.sousa at intel.com>
+ /mt/dim checkpatch caa511d74cfe1960912443997a75a3e4abc67dbb drm-intel
d17a37b85fd4 drm/xe/mcr: Use Xe2_LPM steering tables for Xe2_HPM
b66d54f03df6 drm/xe/xe2: Extend performance tuning to media GT
9f47d17be30e drm/xe/xe2: Assume tuning settings also apply for future media GT
249f723c65bd drm/xe/xe2: Add performance tuning for L3 cache flushing