[PATCH v3 4/4] drm/xe/xe2: Add performance tuning for L3 cache flushing

[Upadhyay, Tejas]

> -----Original Message-----
> From: Sousa, Gustavo <gustavo.sousa at intel.com>
> Sent: Saturday, September 21, 2024 2:43 AM
> To: intel-xe at lists.freedesktop.org
> Cc: Roper, Matthew D <matthew.d.roper at intel.com>; Pottumuttu, Sai Teja
> <sai.teja.pottumuttu at intel.com>; Upadhyay, Tejas
> <tejas.upadhyay at intel.com>
> Subject: [PATCH v3 4/4] drm/xe/xe2: Add performance tuning for L3 cache
> flushing
> 
> A recommended performance tuning for LNL related to L3 cache flushing was
> recently introduced in Bspec. Implement it.
> 
> Unlike the other existing tuning settings, we limit this one for LNL only, since
> there is no info about whether this would be applicable to other platforms
> yet. In the future we can come back and use IP version ranges if applicable.
> 
> v2:
>   - Fix reference to Bspec. (Sai Teja, Tejas)
>   - Use correct register name for "Tuning: L3 RW flush all Cache". (Sai
>     Teja)
>   - Use SCRATCH3_LBCF (with the underscore) for better readability.
> v3:
>   - Limit setting to LNL only. (Matt)
> 
> Bspec: 72161
> Cc: Sai Teja Pottumuttu <sai.teja.pottumuttu at intel.com>
> Cc: Tejas Upadhyay <tejas.upadhyay at intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa at intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +++++
>  drivers/gpu/drm/xe/xe_tuning.c       | 8 ++++++++
>  2 files changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 07315eb72eff..8d8f6a113a86 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -388,6 +388,9 @@
>  #define L3SQCREG3				XE_REG_MCR(0xb108)
>  #define   COMPPWOVERFETCHEN			REG_BIT(28)
> 
> +#define SCRATCH3_LBCF
> 	XE_REG_MCR(0xb154)
> +#define   RWFLUSHALLEN				REG_BIT(17)
> +
>  #define XEHP_L3SQCREG5
> 	XE_REG_MCR(0xb158)
>  #define   L3_PWM_TIMER_INIT_VAL_MASK		REG_GENMASK(9, 0)
> 
> @@ -405,6 +408,8 @@
> 
>  #define XE2LPM_L3SQCREG3			XE_REG_MCR(0xb608)
> 
> +#define XE2LPM_SCRATCH3_LBCF
> 	XE_REG_MCR(0xb654)
> +
>  #define XE2LPM_L3SQCREG5			XE_REG_MCR(0xb658)
> 
>  #define XE2_TDF_CTRL				XE_REG(0xb418)
> diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
> index 230369f108ab..d449de0fb6ec 100644
> --- a/drivers/gpu/drm/xe/xe_tuning.c
> +++ b/drivers/gpu/drm/xe/xe_tuning.c
> @@ -75,6 +75,14 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>  	  XE_RTP_ACTIONS(FIELD_SET(STATELESS_COMPRESSION_CTRL,
> UNIFIED_COMPRESSION_FORMAT,
> 
> REG_FIELD_PREP(UNIFIED_COMPRESSION_FORMAT, 0)))
>  	},
> +	{ XE_RTP_NAME("Tuning: L3 RW flush all Cache"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION(2004)),
> +	  XE_RTP_ACTIONS(SET(SCRATCH3_LBCF, RWFLUSHALLEN))
> +	},
> +	{ XE_RTP_NAME("Tuning: L3 RW flush all cache - media"),
> +	  XE_RTP_RULES(MEDIA_VERSION(2000)),
> +	  XE_RTP_ACTIONS(SET(XE2LPM_SCRATCH3_LBCF, RWFLUSHALLEN))
> +	},

Reviewed-by: Tejas Upadhyay <tejas.upadhyay at intel.com>

Tejas
> 
>  	{}
>  };
> --
> 2.46.1