✗ CI.checkpatch: warning for drm/i915: Use DSB for plane/color management commits

[Patchwork]

== Series Details ==

Series: drm/i915: Use DSB for plane/color management commits
URL   : https://patchwork.freedesktop.org/series/139341/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 47d1986acd00920d5507baba894757a576b8ca12
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date:   Mon Sep 30 20:04:15 2024 +0300

    drm/i915/dsb: Use DSB for plane/color management updates
    
    Push regular plane/color management updates to the DSB,
    if other constraints allow it.
    
    The first part of the sequence will go as follows:
    - CPU will kick off DSB0 immediately
    - DSB0 writes double bufferd non-arming registers
    - DSB0 evades the vblank
    - DSB0 writes double buffered arming registers
    
    If no color management updates is needed we follow that up with:
    - DSB0 waits for the undelayed vblank
    - DSB0 waits for the delayed vblank (usec wait)
    - DSB0 emits an interrupt which will cause the CPU to complete the commit
    
    If color management update is needed:
    - DSB0 will start DSB1 with wait for undelayed vblank
    - DSB0 will in parallel perform the force DEwake tricks
    - DSB1 writes single buffered LUT registers
    - DSB1 waits for the delayed vblank (usec wait)
    - DSB1 emits an interrupt which will cause the CPU to complete the commit
    
    With this sequence we don't need to increase the vblank delay
    to make room for register programming during vblank, which is
    a good thing for high refresh rate display. But I'll need to
    still think of some way to eliminate VRR commit completion
    related races under this scheme.
    
    Stuff that isn't ready for DSB yet:
    - modesets (potentially we could do
      at least the plane enabling via DSB)
    - fastsets
    - VRR
    - PSR
    - scalers
    - async flips
    
    Reviewed-by: Animesh Manna <animesh.manna at intel.com>
    Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
+ /mt/dim checkpatch 4e4d7873ac763aa0bd9207ea9ec2b89bb52a6fe1 drm-intel
cfa53fe8197a drm/i915/dsb: Avoid reads of the DSB buffer for indexed register writes
9ab6afa1a942 drm/i915: Prepare clear color before wait_for_dependencies()
87528053b7b5 drm/i915/dsb: Generate the DSB buffer in commit_tail()
a5bb1a5618e8 drm/i915/dsb: Enable programmable DSB interrupt
cf6d6bf7158d drm/i915/dsb: Introduce intel_dsb_vblank_evade()
1eea038a7f93 drm/i915/dsb: Introduce intel_dsb_wait_usec()
df5eb4fcbbc6 drm/i915/dsb: Introduce intel_dsb_wait_vblanks()
0022b8561371 drm/i915: Introduce intel_scanlines_to_usecs()
3c5a7173a0e0 drm/i915/dsb: Introduce intel_dsb_wait_vblank_delay()
1ba3124af292 drm/i915: Extract intel_crtc_prepare_vblank_event()
b74277d2702b drm/i915: Plumb 'dsb' all way to the plane hooks
-:442: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#442: FILE: drivers/gpu/drm/i915/display/intel_cursor.c:632:
+				   skl_cursor_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));

-:908: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#908: FILE: drivers/gpu/drm/i915/display/skl_universal_plane.c:740:
+				   skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));

total: 0 errors, 2 warnings, 0 checks, 1215 lines checked
d5196f05b460 drm/i915: Plumb 'dsb' all way to the color commit hooks
47d1986acd00 drm/i915/dsb: Use DSB for plane/color management updates