[PATCH v5 11/16] drm/xe: Reduce DPT table alignment as in i915

[Ville Syrjälä]

On Thu, Apr 03, 2025 at 08:03:11PM +0100, Tvrtko Ursulin wrote:
> There is some magic going on with DPT alignment values which are

The "magic" is just that we define the alignment in terms of the DPT
address space, and to translate that back into the GGTT address space
we just divide by 512 (page size / PTE size).

This does look to be interestin in the GGTT alignment so this looks
correct to me.

Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

> multiplied by 512, and then for specifically pinning the DPT table
> scaled back down.
> 
> Make xe do it in the same way as i915.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at igalia.com>
> ---
>  drivers/gpu/drm/xe/display/xe_fb_pin.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> index 1538e2b02f89..1ccb4e563bba 100644
> --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
> +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> @@ -327,7 +327,7 @@ static struct i915_vma *__xe_pin_fb_vma(const struct intel_framebuffer *fb,
>  
>  	vma->bo = bo;
>  	if (intel_fb_uses_dpt(&fb->base))
> -		ret = __xe_pin_fb_vma_dpt(fb, view, vma, alignment);
> +		ret = __xe_pin_fb_vma_dpt(fb, view, vma, alignment / 512);
>  	else
>  		ret = __xe_pin_fb_vma_ggtt(fb, view, vma,  alignment);
>  	if (ret)
> -- 
> 2.48.0

-- 
Ville Syrjälä
Intel