[PATCH v2 06/11] drm/i915/psr: Add mechanism to notify PSR of pipe enable/disable

[Kahola, Mika]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Jouni
> Högander
> Sent: Monday, 17 March 2025 10.19
> To: intel-gfx at lists.freedesktop.org; intel-xe at lists.freedesktop.org
> Cc: Hogander, Jouni <jouni.hogander at intel.com>
> Subject: [PATCH v2 06/11] drm/i915/psr: Add mechanism to notify PSR of pipe
> enable/disable
> 
> We need to apply/remove workaround for underrun on idle PSR HW issue
> (Wa_16025596647) when new pipe is enabled or pipe is getting disabled. This
> patch implements mechanism to notify PSR about pipe enable/disable and
> applies/removes the workaround using this notification.
> 
> Bspec: 74151
> 

Reviewed-by: Mika Kahola <mika.kahola at intel.com>

> Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 106 +++++++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_psr.h |   2 +
>  2 files changed, 108 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index a3946eef44f0d..4b62d5832cbfa 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -26,6 +26,7 @@
>  #include <drm/drm_atomic_helper.h>
>  #include <drm/drm_damage_helper.h>
>  #include <drm/drm_debugfs.h>
> +#include <drm/drm_vblank.h>
> 
>  #include "i915_drv.h"
>  #include "i915_reg.h"
> @@ -3664,6 +3665,111 @@ void intel_psr_unlock(const struct intel_crtc_state
> *crtc_state)
>  	}
>  }
> 
> +/* Wa_16025596647 */
> +static void psr1_apply_underrun_on_idle_wa_locked(struct intel_dp *intel_dp,
> +						  bool dc5_dc6_blocked)
> +{
> +	struct intel_display *display = to_intel_display(intel_dp);
> +	u32 val;
> +
> +	if (dc5_dc6_blocked)
> +		val = DMC_EVT_CTL_ENABLE | DMC_EVT_CTL_RECURRING |
> +			REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
> +				       DMC_EVT_CTL_TYPE_EDGE_0_1) |
> +			REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
> +				       DMC_EVT_CTL_EVENT_ID_VBLANK_A);
> +	else
> +		val = REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
> +				     DMC_EVT_CTL_EVENT_ID_FALSE) |
> +			REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
> +				       DMC_EVT_CTL_TYPE_EDGE_0_1);
> +
> +	intel_de_write(display, MTL_PIPEDMC_EVT_CTL_4(intel_dp->psr.pipe),
> +		       val);
> +}
> +
> +/* Wa_16025596647 */
> +static bool is_dc5_dc6_blocked(struct intel_dp *intel_dp) {
> +	struct intel_display *display = to_intel_display(intel_dp);
> +	u32 current_dc_state =
> intel_display_power_get_current_dc_state(display);
> +	struct drm_vblank_crtc *vblank =
> +&display->drm->vblank[intel_dp->psr.pipe];
> +
> +	return (current_dc_state != DC_STATE_EN_UPTO_DC5 &&
> +		current_dc_state != DC_STATE_EN_UPTO_DC6) ||
> +		intel_dp->psr.active_non_psr_pipes ||
> +		READ_ONCE(vblank->enabled);
> +}
> +
> +/* Wa_16025596647 */
> +static void intel_psr_apply_underrun_on_idle_wa_locked(struct intel_dp
> +*intel_dp) {
> +	bool dc5_dc6_blocked;
> +
> +	if (!intel_dp->psr.active)
> +		return;
> +
> +	dc5_dc6_blocked = is_dc5_dc6_blocked(intel_dp);
> +
> +	if (intel_dp->psr.sel_update_enabled)
> +		psr2_program_idle_frames(intel_dp, dc5_dc6_blocked ? 0 :
> +					 psr_compute_idle_frames(intel_dp));
> +	else
> +		psr1_apply_underrun_on_idle_wa_locked(intel_dp,
> dc5_dc6_blocked); }
> +
> +/**
> + * intel_psr_notify_pipe_change - Notify PSR about enable/disable of a
> +pipe
> + * @state: intel atomic state
> + * @crtc: intel crtc
> + * @enable: enable/disable
> + *
> + * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to
> +apply
> + * remove the workaround when pipe is getting enabled/disabled  */ void
> +intel_psr_notify_pipe_change(struct intel_atomic_state *state,
> +				  struct intel_crtc *crtc, bool enable) {
> +	struct intel_display *display = to_intel_display(state);
> +	struct intel_encoder *encoder;
> +
> +	if (DISPLAY_VER(display) != 20 &&
> +	    !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))
> +		return;
> +
> +	for_each_intel_encoder_with_psr(display->drm, encoder) {
> +		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +		u8 active_non_psr_pipes;
> +
> +		mutex_lock(&intel_dp->psr.lock);
> +
> +		if (!intel_dp->psr.enabled || intel_dp-
> >psr.panel_replay_enabled)
> +			goto unlock;
> +
> +		active_non_psr_pipes = intel_dp->psr.active_non_psr_pipes;
> +
> +		if (enable)
> +			active_non_psr_pipes |= BIT(crtc->pipe);
> +		else
> +			active_non_psr_pipes &= ~BIT(crtc->pipe);
> +
> +		if (active_non_psr_pipes == intel_dp->psr.active_non_psr_pipes)
> +			goto unlock;
> +
> +		if ((enable && intel_dp->psr.active_non_psr_pipes) ||
> +		    (!enable && !intel_dp->psr.active_non_psr_pipes)) {
> +			intel_dp->psr.active_non_psr_pipes =
> active_non_psr_pipes;
> +			goto unlock;
> +		}
> +
> +		intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes;
> +
> +		intel_psr_apply_underrun_on_idle_wa_locked(intel_dp);
> +unlock:
> +		mutex_unlock(&intel_dp->psr.lock);
> +	}
> +}
> +
>  static void
>  psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)  { diff --git
> a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index a43a374cff550..273e70a50915c 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -60,6 +60,8 @@ void intel_psr2_program_trans_man_trk_ctl(struct
> intel_dsb *dsb,  void intel_psr_pause(struct intel_dp *intel_dp);  void
> intel_psr_resume(struct intel_dp *intel_dp);  bool
> intel_psr_needs_block_dc_vblank(const struct intel_crtc_state *crtc_state);
> +void intel_psr_notify_pipe_change(struct intel_atomic_state *state,
> +				  struct intel_crtc *crtc, bool enable);
>  bool intel_psr_link_ok(struct intel_dp *intel_dp);
> 
>  void intel_psr_lock(const struct intel_crtc_state *crtc_state);
> --
> 2.43.0