[PATCH v2 2/3] drm/xe: Expose PCIe Gen4 downspeed attributes
Raag Jadav
raag.jadav at intel.com
Wed Apr 16 15:26:22 UTC 2025
On Wed, Apr 16, 2025 at 08:22:38PM +0530, Riana Tauro wrote:
> On 4/16/2025 4:28 PM, Raag Jadav wrote:
> > On Wed, Apr 16, 2025 at 03:36:55PM +0530, Riana Tauro wrote:
> > > Hi Raag
> > >
> > > On 4/3/2025 11:17 PM, Raag Jadav wrote:
> > > > Expose sysfs attributes for PCIe Gen4 downspeed capability and status.
...
> > > > +static ssize_t
> > > > +pcie_gen4_downspeed_status_show(struct device *dev, struct device_attribute *attr, char *buf)
> > > > +{
> > > > + struct pci_dev *pdev = to_pci_dev(dev);
> > > > + struct xe_device *xe = pdev_to_xe_device(pdev);
> > > > + u32 val;
> > > > + int ret;
> > > > +
> > > > + xe_pm_runtime_get(xe);
> > > > + ret = xe_pcode_read(xe_device_get_root_tile(xe), PCODE_MBOX(DGFX_PCODE_STATUS,
> > > > + DGFX_GET_INIT_STATUS, 0), &val, NULL);
> > > indentation
> >
> > Can you please elaborate? Shouldn't it follow the parentheses?
> yeah it should. DGFX_GET_INIT_STATUS should follow PCODE_MBOX parenthesis
>
> or align PCODE_MBOX instead
>
> ret = xe_pcode_read(xe_device_get_root_tile(xe),
> PCODE_MBOX...
Which means we should change it in hwmon as well?
Raag
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