[PATCH v2 2/3] drm/xe: Expose PCIe Gen4 downspeed attributes
Raag Jadav
raag.jadav at intel.com
Thu Apr 17 07:48:09 UTC 2025
On Thu, Apr 17, 2025 at 10:47:19AM +0530, Riana Tauro wrote:
> On 4/16/2025 8:56 PM, Raag Jadav wrote:
> > On Wed, Apr 16, 2025 at 08:22:38PM +0530, Riana Tauro wrote:
> > > On 4/16/2025 4:28 PM, Raag Jadav wrote:
> > > > On Wed, Apr 16, 2025 at 03:36:55PM +0530, Riana Tauro wrote:
> > > > > Hi Raag
> > > > >
> > > > > On 4/3/2025 11:17 PM, Raag Jadav wrote:
> > > > > > Expose sysfs attributes for PCIe Gen4 downspeed capability and status.
> >
> > ...
> >
> > > > > > +static ssize_t
> > > > > > +pcie_gen4_downspeed_status_show(struct device *dev, struct device_attribute *attr, char *buf)
> > > > > > +{
> > > > > > + struct pci_dev *pdev = to_pci_dev(dev);
> > > > > > + struct xe_device *xe = pdev_to_xe_device(pdev);
> > > > > > + u32 val;
> > > > > > + int ret;
> > > > > > +
> > > > > > + xe_pm_runtime_get(xe);
> > > > > > + ret = xe_pcode_read(xe_device_get_root_tile(xe), PCODE_MBOX(DGFX_PCODE_STATUS,
> > > > > > + DGFX_GET_INIT_STATUS, 0), &val, NULL);
> > > > > indentation
> > > >
> > > > Can you please elaborate? Shouldn't it follow the parentheses?
> > > yeah it should. DGFX_GET_INIT_STATUS should follow PCODE_MBOX parenthesis
> > >
> > > or align PCODE_MBOX instead
> > >
> > > ret = xe_pcode_read(xe_device_get_root_tile(xe),
> > > PCODE_MBOX...
This'll warrant a third line which we can easily avoid here.
> > Which means we should change it in hwmon as well?
> Not sure about hwmon. checkpatch is also mentioning the same
>
> -:89: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
> #89: FILE: drivers/gpu/drm/xe/xe_device_sysfs.c:130:
> ret = xe_pcode_read(xe_device_get_root_tile(xe),
> PCODE_MBOX(DGFX_PCODE_STATUS,
> DGFX_GET_INIT_STATUS, 0), &val, NULL);
Yes, it complains about a lot of things but it's referred as a general
guidance than a hard rule.
https://lore.kernel.org/all/CAHk-=wgfzPOao+Rbq4aSitQ2gPaZ9PPGbR290X4BikD_W8ZcUg@mail.gmail.com/
Raag
More information about the Intel-xe
mailing list