[PATCH v2] drm/i915/display: Ensure enough lines between delayed VBlank and VBlank

[Jouni Högander]

To deterministically capture the transition of the state machine going from
SRDOFFACK to IDLE, the delayed V. Blank should be at least one line after
the non-delayed V. Blank.

Ensure this by following instructions from Bspec.

v2: apply limits only when needed (VRR TG vs. Legacy TG)

Bspec: 69897
Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 23 ++++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_vrr.c     | 22 +++++++++++++++++--
 2 files changed, 41 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 33c09999c42e0..eed34d634b104 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2631,6 +2631,23 @@ transcoder_has_vrr(const struct intel_crtc_state *crtc_state)
 	return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder);
 }
 
+static u32 min_context_latency(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	/*
+	 * Comment on SRD_STATUS register in Bspec:
+	 *
+	 * To deterministically capture the transition of the state machine
+	 * going from SRDOFFACK to IDLE, the delayed V. Blank should be at least
+	 * one line after the non-delayed V. Blank.
+	 *
+	 * Legacy TG: TRANS_SET_CONTEXT_LATENCY > 0
+	 */
+	return intel_vrr_always_use_vrr_tg(display) ||
+		crtc_state->vrr.enable ? 0 : 1;
+}
+
 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -2671,7 +2688,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 	if (DISPLAY_VER(display) >= 13) {
 		intel_de_write(display,
 			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
-			       crtc_vblank_start - crtc_vdisplay);
+			       max(crtc_vblank_start - crtc_vdisplay,
+				   min_context_latency(crtc_state)));
 
 		/*
 		 * VBLANK_START not used by hw, just clear it
@@ -2748,7 +2766,8 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
 	if (DISPLAY_VER(display) >= 13) {
 		intel_de_write(display,
 			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
-			       crtc_vblank_start - crtc_vdisplay);
+			       max(crtc_vblank_start - crtc_vdisplay,
+				   min_context_latency(crtc_state)));
 
 		/*
 		 * VBLANK_START not used by hw, just clear it
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index c6565baf815a1..10446f4a74d08 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -422,8 +422,26 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
 		return;
 
 	if (DISPLAY_VER(display) >= 13) {
-		crtc_state->vrr.guardband =
-			crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start;
+		/*
+		 * Comment on SRD_STATUS register in Bspec:
+		 *
+		 * To deterministically capture the transition of the state
+		 * machine going from SRDOFFACK to IDLE, the delayed V. Blank
+		 * should be at least one line after the non-delayed V. Blank.
+		 * This can be done by ensuring the VRR Guardband programming is
+		 * less than the non-delayed V. Blank.
+		 *
+		 * TRANS_VRR_CTL[ VRR Guardband ] < (TRANS_VRR_VMAX[ VRR Vmax ]
+		 * - TRANS_VTOTAL[ Vertical Active ])
+		 */
+		if (intel_vrr_always_use_vrr_tg(display) || crtc_state->vrr.enable)
+			crtc_state->vrr.guardband = min(crtc_state->vrr.vmin -
+							adjusted_mode->crtc_vblank_start,
+							crtc_state->vrr.vmax -
+							adjusted_mode->vdisplay - 1);
+		else
+			crtc_state->vrr.guardband = crtc_state->vrr.vmin -
+				adjusted_mode->crtc_vblank_start;
 	} else {
 		/* hardware imposes one extra scanline somewhere */
 		crtc_state->vrr.pipeline_full =
-- 
2.43.0