✓ CI.checkpatch: success for drm/i915/display: Ensure enough lines between delayed VBlank and VBlank (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Ensure enough lines between delayed VBlank and VBlank (rev2)
URL   : https://patchwork.freedesktop.org/series/147935/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
13a92ce9fd458ebd6064f23cec8c39c53d02ed26
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 74fd22d59cbb4beb6bf464eec444e549e5c5e4bd
Author: Jouni Högander <jouni.hogander at intel.com>
Date:   Tue Apr 22 12:17:46 2025 +0300

    drm/i915/display: Ensure enough lines between delayed VBlank and VBlank
    
    To deterministically capture the transition of the state machine going from
    SRDOFFACK to IDLE, the delayed V. Blank should be at least one line after
    the non-delayed V. Blank.
    
    Ensure this by following instructions from Bspec.
    
    v2: apply limits only when needed (VRR TG vs. Legacy TG)
    
    Bspec: 69897
    Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
+ /mt/dim checkpatch 07a9e9039f712f604032443a9bd9af283d524acc drm-intel
74fd22d59cbb drm/i915/display: Ensure enough lines between delayed VBlank and VBlank