[PATCH v3 06/13] drm/i915/psr: Block PKG C-State when enabling PSR

Kahola, Mika mika.kahola at intel.com
Tue Apr 22 09:38:49 UTC 2025


> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Jouni
> Högander
> Sent: Monday, 14 April 2025 13.05
> To: intel-gfx at lists.freedesktop.org; intel-xe at lists.freedesktop.org
> Cc: Hogander, Jouni <jouni.hogander at intel.com>
> Subject: [PATCH v3 06/13] drm/i915/psr: Block PKG C-State when enabling PSR
> 
> Block PKG C-State when enabling PSR when enabling PSR as described in
> workaround for underrun on idle PSR HW issue (Wa_16025596647).
> 
> v2: use intel_dmc_block_pkgc instead of directly writing dmc register
> 
> Bspec: 74151

Reviewed-by: Mika Kahola <mika.kahola at intel.com>

> Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 20d53292c3b3..44adee087350 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -38,6 +38,7 @@
>  #include "intel_display_irq.h"
>  #include "intel_display_rpm.h"
>  #include "intel_display_types.h"
> +#include "intel_dmc.h"
>  #include "intel_dp.h"
>  #include "intel_dp_aux.h"
>  #include "intel_frontbuffer.h"
> @@ -1951,6 +1952,12 @@ static void intel_psr_enable_source(struct intel_dp
> *intel_dp,
>  			intel_de_rmw(display, CLKGATE_DIS_MISC, 0,
>  				     CLKGATE_DIS_MISC_DMASC_GATING_DIS);
>  	}
> +
> +	/* Wa_16025596647 */
> +	if ((DISPLAY_VER(display) == 20 ||
> +	     IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
> +	    !intel_dp->psr.panel_replay_enabled)
> +		intel_dmc_block_pkgc(display, intel_dp->psr.pipe, true);
>  }
> 
>  static bool psr_interrupt_error_check(struct intel_dp *intel_dp) @@ -2175,6
> +2182,12 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>  					   DP_RECEIVER_ALPM_CONFIG, 0);
>  	}
> 
> +	/* Wa_16025596647 */
> +	if ((DISPLAY_VER(display) == 20 ||
> +	     IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
> +	    !intel_dp->psr.panel_replay_enabled)
> +		intel_dmc_block_pkgc(display, intel_dp->psr.pipe, false);
> +
>  	intel_dp->psr.enabled = false;
>  	intel_dp->psr.panel_replay_enabled = false;
>  	intel_dp->psr.sel_update_enabled = false;
> --
> 2.43.0



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