[PATCH v2 04/13] drm/i915/vrr: Add enable/disable calls for DC Balance
Nautiyal, Ankit K
ankit.k.nautiyal at intel.com
Wed Apr 23 07:01:49 UTC 2025
On 4/21/2025 9:18 PM, Mitul Golani wrote:
> Add enable/disable calls along with required hw registers
> for DC balance enablement.
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani at intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 7 ++
> drivers/gpu/drm/i915/display/intel_dmc_regs.h | 71 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_vrr.c | 29 ++++++++
> drivers/gpu/drm/i915/display/intel_vrr_regs.h | 10 +++
> 4 files changed, 117 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 94468a9d2e0d..126d54e6a393 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1307,6 +1307,13 @@ struct intel_crtc_state {
> u8 pipeline_full;
> u16 flipline, vmin, vmax, guardband;
> u32 vsync_end, vsync_start;
> + struct {
> + bool enable;
> + u16 vmin, vmax;
> + u16 guardband, slope;
> + u16 max_increase, max_decrease;
> + u16 vblank_target;
> + } dc_balance;
> } vrr;
>
> /* Content Match Refresh Rate state */
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> index 1bf446f96a10..39e4f70005ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> @@ -103,4 +103,75 @@
> #define DMC_WAKELOCK_CTL_REQ REG_BIT(31)
> #define DMC_WAKELOCK_CTL_ACK REG_BIT(15)
>
> +#define _PIPEDMC_DCB_CTL_A 0x5F1A0
These are again added in Patch #9
> +#define _PIPEDMC_DCB_CTL_B 0x5F5A0
> +#define _PIPEDMC_DCB_CTL_C 0x5F9A0
> +#define _PIPEDMC_DCB_CTL_D 0x5FDA0
> +#define _PIPEDMC_DCB_CTL_E 0x551A0
> +#define _PIPEDMC_DCB_CTL_F 0x555A0
> +#define PIPEDMC_DCB_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_CTL_A)
> +#define PIPEDMC_ADAPTIVE_DCB_ENABLE REG_BIT(31)
> +
> +#define _PIPEDMC_DCB_VBLANK_A 0x5F1BC
> +#define _PIPEDMC_DCB_VBLANK_B 0x5F5BC
> +#define _PIPEDMC_DCB_VBLANK_C 0x5F9BC
> +#define _PIPEDMC_DCB_VBLANK_D 0x5FDBC
> +#define _PIPEDMC_DCB_VBLANK_E 0x551BC
> +#define _PIPEDMC_DCB_VBLANK_F 0x555BC
> +#define PIPEDMC_DCB_VBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_VBLANK_A)
> +
> +#define _PIPEDMC_DCB_SLOPE_A 0x5F1B8
> +#define _PIPEDMC_DCB_SLOPE_B 0x5F5B8
> +#define _PIPEDMC_DCB_SLOPE_C 0x5F9B8
> +#define _PIPEDMC_DCB_SLOPE_D 0x5FDB8
> +#define _PIPEDMC_DCB_SLOPE_E 0x551B8
> +#define _PIPEDMC_DCB_SLOPE_F 0x555B8
> +#define PIPEDMC_DCB_SLOPE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_SLOPE_A)
> +
> +#define _PIPEDMC_DCB_GUARDBAND_A 0x5F1B4
> +#define _PIPEDMC_DCB_GUARDBAND_B 0x5F5B4
> +#define _PIPEDMC_DCB_GUARDBAND_C 0x5F9B4
> +#define _PIPEDMC_DCB_GUARDBAND_D 0x5FDB4
> +#define _PIPEDMC_DCB_GUARDBAND_E 0x551B4
> +#define _PIPEDMC_DCB_GUARDBAND_F 0x555B4
> +#define PIPEDMC_DCB_GUARDBAND(dev_priv, trans) _MMIO_TRANS2(dev_priv, \
> + trans, \
> + _PIPEDMC_DCB_GUARDBAND_A)
> +
> +#define _PIPEDMC_DCB_MAX_INCREASE_A 0x5F1AC
> +#define _PIPEDMC_DCB_MAX_INCREASE_B 0x5F5AC
> +#define _PIPEDMC_DCB_MAX_INCREASE_C 0x5F9AC
> +#define _PIPEDMC_DCB_MAX_INCREASE_D 0x5FDAC
> +#define _PIPEDMC_DCB_MAX_INCREASE_E 0x551AC
> +#define _PIPEDMC_DCB_MAX_INCREASE_F 0x555AC
> +#define PIPEDMC_DCB_MAX_INCREASE(dev_priv, trans) _MMIO_TRANS2(dev_priv, \
> + trans, \
> + _PIPEDMC_DCB_MAX_INCREASE_A)
> +
> +#define _PIPEDMC_DCB_MAX_DECREASE_A 0x5F1B0
> +#define _PIPEDMC_DCB_MAX_DECREASE_B 0x5F5B0
> +#define _PIPEDMC_DCB_MAX_DECREASE_C 0x5F9B0
> +#define _PIPEDMC_DCB_MAX_DECREASE_D 0x5FDB0
> +#define _PIPEDMC_DCB_MAX_DECREASE_E 0x551B0
> +#define _PIPEDMC_DCB_MAX_DECREASE_F 0x555B0
> +#define PIPEDMC_DCB_MAX_DECREASE(dev_priv, trans) _MMIO_TRANS2(dev_priv, \
> + trans, \
> + _PIPEDMC_DCB_MAX_DECREASE_A)
> +
> +#define _PIPEDMC_DCB_VMIN_A 0x5F1A4
> +#define _PIPEDMC_DCB_VMIN_B 0x5F5A4
> +#define _PIPEDMC_DCB_VMIN_C 0x5F9A4
> +#define _PIPEDMC_DCB_VMIN_D 0x5FDA4
> +#define _PIPEDMC_DCB_VMIN_E 0x551A4
> +#define _PIPEDMC_DCB_VMIN_F 0x555A4
> +#define PIPEDMC_DCB_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_VMIN_A)
> +
> +#define _PIPEDMC_DCB_VMAX_A 0x5F1A8
> +#define _PIPEDMC_DCB_VMAX_B 0x5F5A8
> +#define _PIPEDMC_DCB_VMAX_C 0x5F9A8
> +#define _PIPEDMC_DCB_VMAX_D 0x5FDA8
> +#define _PIPEDMC_DCB_VMAX_E 0x551A8
> +#define _PIPEDMC_DCB_VMAX_F 0x555A8
> +#define PIPEDMC_DCB_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_VMAX_A)
> +
> #endif /* __INTEL_DMC_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 1c0eaa08927b..c4fb78d86ab0 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -10,6 +10,7 @@
> #include "intel_de.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> +#include "intel_dmc_regs.h"
> #include "intel_vrr.h"
> #include "intel_vrr_regs.h"
>
> @@ -601,6 +602,23 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
> VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
> }
> }
> +
> + if (crtc_state->vrr.dc_balance.enable && HAS_DC_BALANCE(display)) {
> + intel_de_write(display, PIPEDMC_DCB_VMIN(display, cpu_transcoder),
> + crtc_state->vrr.dc_balance.vmin - 1);
> + intel_de_write(display, PIPEDMC_DCB_VMAX(display, cpu_transcoder),
> + crtc_state->vrr.dc_balance.vmax - 1);
> + intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(display, cpu_transcoder),
> + crtc_state->vrr.dc_balance.max_increase);
> + intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(display, cpu_transcoder),
> + crtc_state->vrr.dc_balance.max_decrease);
> + intel_de_write(display, PIPEDMC_DCB_GUARDBAND(display, cpu_transcoder),
> + crtc_state->vrr.dc_balance.guardband);
> + intel_de_write(display, PIPEDMC_DCB_SLOPE(display, cpu_transcoder),
> + crtc_state->vrr.dc_balance.slope);
> + intel_de_write(display, PIPEDMC_DCB_VBLANK(display, cpu_transcoder),
> + crtc_state->vrr.dc_balance.vblank_target);
> + }
> }
>
> void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
> @@ -611,6 +629,17 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
> if (!old_crtc_state->vrr.enable)
> return;
>
> + if (old_crtc_state->vrr.dc_balance.enable && HAS_DC_BALANCE(display)) {
> + intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(display, cpu_transcoder), 0);
> + intel_de_write(display, PIPEDMC_DCB_VMIN(display, cpu_transcoder), 0);
> + intel_de_write(display, PIPEDMC_DCB_VMAX(display, cpu_transcoder), 0);
> + intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(display, cpu_transcoder), 0);
> + intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(display, cpu_transcoder), 0);
> + intel_de_write(display, PIPEDMC_DCB_GUARDBAND(display, cpu_transcoder), 0);
> + intel_de_write(display, PIPEDMC_DCB_SLOPE(display, cpu_transcoder), 0);
> + intel_de_write(display, PIPEDMC_DCB_VBLANK(display, cpu_transcoder), 0);
> + }
> +
> if (!intel_vrr_always_use_vrr_tg(display)) {
> intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> trans_vrr_ctl(old_crtc_state));
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> index 2214c10d4084..2db477325c83 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> @@ -53,6 +53,16 @@
> #define VRR_FLIPLINE_DCB_MASK REG_GENMASK(19, 0)
> #define VRR_VMAX_DCB_MASK REG_GENMASK(19, 0)
>
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A 0x604C0
These are again added in Patch#10.
I think lets have a separate patch where new members are introduced.
Regards,
Ankit
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B 0x614C0
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_C 0x624C0
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_D 0x634C0
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_E 0x6B4C0
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_F 0x6C4C0
> +#define TRANS_ADAPTIVE_SYNC_DCB_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, \
> + trans, \
> + _TRANS_ADAPTIVE_SYNC_DCB_CTL_A)
> +
> #define _TRANS_VRR_CTL_A 0x60420
> #define _TRANS_VRR_CTL_B 0x61420
> #define _TRANS_VRR_CTL_C 0x62420
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