[PATCH 1/2] drm/xe/guc: Add a missing H2G error code definition

[Michal Wajdeczko]

On 26.03.2025 20:32, John.C.Harrison at Intel.com wrote:
> From: John Harrison <John.C.Harrison at Intel.com>
> 
> These error codes are not actually used in the driver but it is
> extremely useful to have them available to understand error messages.
> The most recent spate of FAST_REQ errors being reported have been
> about error 0x30C, so add in the missing define for that.

maybe we should try to sync more missing error codes than this only one
that we seen recently, to avoid being surprise another day when some new
unrecognized error will be seen like:

INVALID_CONTEXT_INDEX               = 0x61,
INVALID_CONTEXT_REGISTRATION        = 0x62,
INVALID_ENGINE_ID                   = 0x64,
BUFFER_ALREADY_REGISTERED           = 0x72,
CONTEXT_NOT_REGISTERED              = 0x100,
CONTEXT_ALREADY_REGISTERED          = 0x101,

then above quote "extremely useful to have them available to understand
error messages" will still hold

> 
> Signed-off-by: John Harrison <John.C.Harrison at Intel.com>
> ---
>  drivers/gpu/drm/xe/abi/guc_errors_abi.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/xe/abi/guc_errors_abi.h b/drivers/gpu/drm/xe/abi/guc_errors_abi.h
> index 2c627a21648f..c25ea52a6e61 100644
> --- a/drivers/gpu/drm/xe/abi/guc_errors_abi.h
> +++ b/drivers/gpu/drm/xe/abi/guc_errors_abi.h
> @@ -40,6 +40,7 @@ enum xe_guc_response_status {
>  	XE_GUC_RESPONSE_CTB_NOT_REGISTERED                  = 0x304,
>  	XE_GUC_RESPONSE_CTB_IN_USE                          = 0x305,
>  	XE_GUC_RESPONSE_CTB_INVALID_DESC                    = 0x306,
> +	XE_GUC_RESPONSE_STATUS_HW_TIMEOUT                   = 0x30C,

STATUS seems redundant here, most of other enums don't have it

	XE_GUC_RESPONSE_HW_TIMEOUT

>  	XE_GUC_RESPONSE_CTB_SOURCE_INVALID_DESCRIPTOR       = 0x30D,
>  	XE_GUC_RESPONSE_CTB_DESTINATION_INVALID_DESCRIPTOR  = 0x30E,
>  	XE_GUC_RESPONSE_INVALID_CONFIG_STATE                = 0x30F,

with more error codes added,

Reviewed-by: Michal Wajdeczko <michal.wajdeczko at intel.com>