✗ CI.checkpatch: warning for drm/i915/tc: Fix enabled/disconnected DP-alt sink handling

[Patchwork]

== Series Details ==

Series: drm/i915/tc: Fix enabled/disconnected DP-alt sink handling
URL   : https://patchwork.freedesktop.org/series/152514/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
c298eac5978c38dcc62a70c0d73c91765e7cc296
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit f3f5afd67ee7974ca399d2d2bd7cd317039d7697
Author: Imre Deak <imre.deak at intel.com>
Date:   Tue Aug 5 10:37:00 2025 +0300

    drm/i915/tc: Debug print the pin assignment and max lane count
    
    Debug print the TypeC pin assignment and max lane count value during HW
    readout and after resetting the TypeC mode.
    
    Signed-off-by: Imre Deak <imre.deak at intel.com>
+ /mt/dim checkpatch c79dfb5e415ae8c63601b02f7b3a2082d1a2345b drm-intel
15c0253c3e62 drm/i915/lnl+/tc: Fix handling of an enabled/disconnected dp-alt sink
-:36: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report
#36: 
Reported-by: Charlton Lin <charlton.lin at intel.com>
Tested-by: Khaled Almahallawy <khaled.almahallawy at intel.com>

-:84: WARNING:MISSING_FIXES_TAG: The commit message has 'stable@', perhaps it also needs a 'Fixes:' tag?

total: 0 errors, 2 warnings, 0 checks, 38 lines checked
032f572013d5 drm/i915/icl+/tc: Cache the max lane count value
-:21: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report
#21: 
Reported-by: Charlton Lin <charlton.lin at intel.com>
Tested-by: Khaled Almahallawy <khaled.almahallawy at intel.com>

-:163: WARNING:MISSING_FIXES_TAG: The commit message has 'stable@', perhaps it also needs a 'Fixes:' tag?

total: 0 errors, 2 warnings, 0 checks, 124 lines checked
ee01c9c7d751 drm/i915/lnl+/tc: Fix max lane count HW readout
-:21: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report
#21: 
Reported-by: Charlton Lin <charlton.lin at intel.com>
Tested-by: Khaled Almahallawy <khaled.almahallawy at intel.com>

-:58: WARNING:MISSING_FIXES_TAG: The commit message has 'stable@', perhaps it also needs a 'Fixes:' tag?

total: 0 errors, 2 warnings, 0 checks, 27 lines checked
999f9ca5b2a6 drm/i915/lnl+/tc: Use the cached max lane count value
-:16: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report
#16: 
Reported-by: Charlton Lin <charlton.lin at intel.com>
Tested-by: Khaled Almahallawy <khaled.almahallawy at intel.com>

-:41: WARNING:MISSING_FIXES_TAG: The commit message has 'stable@', perhaps it also needs a 'Fixes:' tag?

total: 0 errors, 2 warnings, 0 checks, 17 lines checked
e9256f6577b4 drm/i915/icl+/tc: Convert AUX powered WARN to a debug message
-:13: WARNING:BAD_REPORTED_BY_LINK: Reported-by: should be immediately followed by Closes: with a URL to the report
#13: 
Reported-by: Charlton Lin <charlton.lin at intel.com>
Tested-by: Khaled Almahallawy <khaled.almahallawy at intel.com>

-:35: WARNING:MISSING_FIXES_TAG: The commit message has 'stable@', perhaps it also needs a 'Fixes:' tag?

total: 0 errors, 2 warnings, 0 checks, 14 lines checked
213152a71f5c drm/i915/tc: Use the cached max lane count value
e5bdd7b6d1be drm/i915/tc: Move getting the power domain before reading DFLEX registers
73a294b9c201 drm/i915/tc: Move asserting the power state after reading TCSS_DDI_STATUS
4ab6879919e7 drm/i915/tc: Add an enum for the TypeC pin assignment
3cf74e647354 drm/i915/tc: Pass pin assignment value around using the pin assignment enum
65d246e04056 drm/i915/tc: Handle pin assignment NONE on all platforms
e20220721ea1 drm/i915/tc: Validate the pin assignment on all platforms
f7a0c8a64d45 drm/i915/tc: Unify the way to get the pin assignment on all platforms
865c2bb16658 drm/i915/tc: Unify the way to get the max lane count value on MTL+
71794b24c2f1 drm/i915/tc: Handle non-TC encoders when getting the pin assignment
895b8c0a12c8 drm/i915/tc: Pass intel_tc_port to internal lane mask/count helpers
b5c6e591aeea dmc/i915/tc: Report pin assignment NONE in TBT-alt mode
ab6b04940979 drm/i915/tc: Cache the pin assignment value
f3f5afd67ee7 drm/i915/tc: Debug print the pin assignment and max lane count