[PATCH v4 10/12] drm/i915/display: Add function to configure LFPS sending

[Jani Nikula]

On Mon, 26 May 2025, Jouni Högander <jouni.hogander at intel.com> wrote:
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 91118d115fd3..75caccb65513 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -3225,6 +3225,37 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder,
>  		intel_cx0pll_enable(encoder, crtc_state);
>  }
>  
> +/*
> + * According to HAS we need to enable MAC Transmitting LFPS in the "PHY Common
> + * Control 0" PIPE register in case of AUX Less ALPM is going to be used. This
> + * function is doing that and is called by link retrain sequence.
> + */
> +void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
> +				 const struct intel_crtc_state *crtc_state)

Commenting after the fact:

Please don't combine "intel_" and platform prefixes like "lnl_" or
"mtl_". The file is a mess wrt naming.

BR,
Jani.



-- 
Jani Nikula, Intel