[CI 12/13] late flush
Tvrtko Ursulin
tvrtko.ursulin at igalia.com
Tue Aug 19 14:38:19 UTC 2025
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at igalia.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 15 ++++-
drivers/gpu/drm/i915/gem/i915_gem_object.h | 5 ++
.../compat-i915-headers/gem/i915_gem_object.h | 3 +
drivers/gpu/drm/xe/display/xe_fb_pin.c | 56 +++++--------------
drivers/gpu/drm/xe/xe_bo_types.h | 4 +-
5 files changed, 39 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c1a3a95c65f0..bdd487f5b3de 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -45,6 +45,7 @@
#include <drm/drm_rect.h>
#include <drm/drm_vblank.h>
+#include "gem/i915_gem_object.h"
#include "g4x_dp.h"
#include "g4x_hdmi.h"
#include "hsw_ips.h"
@@ -7099,7 +7100,7 @@ static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_stat
struct drm_plane *plane;
struct drm_plane_state *new_plane_state;
long ret;
- int i;
+ int i, j;
for_each_new_plane_in_state(&intel_state->base, plane, new_plane_state, i) {
if (new_plane_state->fence) {
@@ -7112,6 +7113,18 @@ static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_stat
new_plane_state->fence = NULL;
}
}
+
+ for_each_new_plane_in_state(&intel_state->base, plane, new_plane_state, i) {
+ if (!new_plane_state->fb)
+ continue;
+
+ for (j = 0; j < new_plane_state->fb->format->num_planes; j++) {
+ if (!new_plane_state->fb->obj[j])
+ continue;
+
+ intel_display_object_sync_flush(new_plane_state->fb->obj[j]);
+ }
+ }
}
static void intel_atomic_dsb_wait_commit(struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 565f8fa330db..c185234924ab 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -772,6 +772,11 @@ void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj);
void i915_gem_object_flush_if_display_locked(struct drm_i915_gem_object *obj);
bool i915_gem_cpu_write_needs_clflush(struct drm_i915_gem_object *obj);
+static inline void intel_display_object_sync_flush(struct drm_gem_object *obj)
+{
+
+}
+
int __must_check
i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
int __must_check
diff --git a/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object.h b/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object.h
index 8a048980ea38..d962e50d42be 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object.h
@@ -5,6 +5,7 @@
#define __I915_GEM_OBJECT_H__
struct dma_fence;
+struct drm_gem_object;
struct i915_sched_attr;
static inline void i915_gem_fence_wait_priority(struct dma_fence *fence,
@@ -12,4 +13,6 @@ static inline void i915_gem_fence_wait_priority(struct dma_fence *fence,
{
}
+void intel_display_object_sync_flush(struct drm_gem_object *obj);
+
#endif
diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index bf600cad0284..e112c01b21a0 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -6,6 +6,7 @@
#include <drm/drm_cache.h>
#include <drm/ttm/ttm_bo.h>
+#include "gem/i915_gem_object.h"
#include "i915_vma.h"
#include "intel_display_core.h"
#include "intel_display_types.h"
@@ -371,44 +372,23 @@ static int __xe_pin_fb_vma_ggtt(const struct intel_framebuffer *fb,
return ret;
}
-static void xe_bo_clflush_auxccs(struct xe_bo *bo,
- const struct i915_gtt_view *view)
+void intel_display_object_sync_flush(struct drm_gem_object *obj)
{
- const struct intel_remapped_info *remap_info = &view->remapped;
- unsigned int i;
+ struct xe_bo *bo = gem_to_xe_bo(obj);
+ int ret;
- if (!IS_ENABLED(CONFIG_X86))
- return;
+ ret = ttm_bo_reserve(&bo->ttm, false, false, NULL);
+ WARN_ON_ONCE(ret);
- if (!static_cpu_has(X86_FEATURE_CLFLUSH))
- return;
+ if (!bo->display_flush)
+ goto unlock;
- for (i = 0; i < ARRAY_SIZE(remap_info->plane); i++) {
- const struct intel_remapped_plane_info *plane =
- &remap_info->plane[i];
- const int size = boot_cpu_data.x86_clflush_size;
- struct sg_table *st = xe_bo_sg(bo);
- struct sg_page_iter sg_iter;
+ drm_clflush_sg(xe_bo_sg(bo));
- if (!plane->width && !plane->height && !plane->linear)
- continue;
+ bo->display_flush = false;
- if (!plane->linear)
- continue;
-
- mb();
- for_each_sgtable_page(st, &sg_iter, plane->offset) {
- struct page *page = sg_page_iter_page(&sg_iter);
- uint8_t *page_virtual;
- unsigned int j;
-
- page_virtual = kmap_local_page(page);
- for (j = 0; j < PAGE_SIZE; j += size)
- clflushopt(page_virtual + j);
- kunmap_local(page_virtual);
- }
- mb();
- }
+unlock:
+ ttm_bo_unreserve(&bo->ttm);
}
static struct i915_vma *__xe_pin_fb_vma(const struct intel_framebuffer *fb,
@@ -420,7 +400,6 @@ static struct i915_vma *__xe_pin_fb_vma(const struct intel_framebuffer *fb,
struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
struct drm_gem_object *obj = intel_fb_bo(&fb->base);
struct xe_bo *bo = gem_to_xe_bo(obj);
- bool first_pin;
int ret;
if (!vma)
@@ -452,9 +431,6 @@ static struct i915_vma *__xe_pin_fb_vma(const struct intel_framebuffer *fb,
if (ret)
goto err;
- first_pin = !bo->display_pin;
- bo->display_pin = true;
-
if (IS_DGFX(xe))
ret = xe_bo_migrate(bo, XE_PL_VRAM0);
else
@@ -476,11 +452,9 @@ static struct i915_vma *__xe_pin_fb_vma(const struct intel_framebuffer *fb,
/*
* Force flush AuxCCS data for non-coherent display access.
*/
- if (first_pin &&
- !xe_bo_is_vram(bo) && !xe_bo_is_stolen(bo) &&
- intel_fb_is_ccs_modifier(fb->base.modifier) &&
- view->type == I915_GTT_VIEW_REMAPPED)
- xe_bo_clflush_auxccs(bo, view);
+ bo->display_flush = !xe_bo_is_vram(bo) && !xe_bo_is_stolen(bo) &&
+ intel_fb_is_ccs_modifier(fb->base.modifier) &&
+ view->type == I915_GTT_VIEW_REMAPPED;
return vma;
diff --git a/drivers/gpu/drm/xe/xe_bo_types.h b/drivers/gpu/drm/xe/xe_bo_types.h
index d5096f7f6f9a..150a54be0b2e 100644
--- a/drivers/gpu/drm/xe/xe_bo_types.h
+++ b/drivers/gpu/drm/xe/xe_bo_types.h
@@ -91,8 +91,8 @@ struct xe_bo {
/** @ccs_cleared */
bool ccs_cleared : 1;
- /** @display_pin: Was it ever pinned to display */
- bool display_pin : 1;
+ /** @display_flush: Is clflush required before first scanout */
+ bool display_flush : 1;
/** @vram_userfault_link: Link into @mem_access.vram_userfault.list */
struct list_head vram_userfault_link;
--
2.48.0
More information about the Intel-xe
mailing list