✗ Xe.CI.Full: failure for AuxCCS handling and render compression modifiers

[Rodrigo Vivi]

On Tue, Feb 04, 2025 at 11:12:45AM +0000, Tvrtko Ursulin wrote:
> 
> + Rodrigo and Jani for possible CI/display insights or adding correct Cc
> please.

+Ville, Uma

I never liked very much the crc checks, but I thought the pipe crc were
more reliable. I had a horrible experience with the edp sink crc in the
past...

more below...

> 
> On 31/01/2025 20:26, Patchwork wrote:
> > igt at kms_flip_tiling@flip-change-tiling at pipe-a-hdmi-a-1-y-rc-ccs-cc-to-y-mc-ccs (NEW):
> > 
> >   * shard-adlp: NOTRUN -> FAIL
> >     <https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144186v1/shard-adlp-2/igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-y-rc-ccs-cc-to-y-mc-ccs.html> +66 other tests fail
> 
> Two things here.
> 
> First it seems to be some sort of a race condition in crc collection and/or
> vblank counter handling. Tests work individually but fail one run in
> sequence. Bad CRC also varies run to run, while visually things look fine to
> me on screen. Also a delay before collecting the crc seems to improve
> things.
> 
> I instrumented things a bit but I don't really understand it. For example
> collecting the reference CRC appears to have some "collect it at the next
> vblank logic", but I am not sure that works correctly. Ie.
> 
> Working case:
> ==========================================
> 
> Getting the reference CRC:
> ------------------------------------------
> (kms_flip_tiling:14174) igt_pipe_crc-DEBUG: crc for vblank 703868, target
> 703869; crc[0]=b82b36e4
> (kms_flip_tiling:14174) igt_pipe_crc-DEBUG: crc for vblank 703869, target
> 703869; crc[0]=b82b36e4
> 
> reference_crc[0]=b82b36e4
> 
> Compare after flip:
> 
> (kms_flip_tiling:14174) igt_pipe_crc-DEBUG: crc for vblank 703870, target
> 703872; crc[0]=b82b36e4
> (kms_flip_tiling:14174) igt_pipe_crc-DEBUG: crc for vblank 703871, target
> 703872; crc[0]=2aa66f1d
> (kms_flip_tiling:14174) igt_pipe_crc-DEBUG: crc for vblank 703872, target
> 703872; crc[0]=b82b36e4
> 
> reference_crc[0]=b82b36e4 crc[0]=b82b36e4
> 
> 
> Failing case:
> ==========================================
> 
> Getting the reference CRC:
> ------------------------------------------
> (kms_flip_tiling:14145) igt_pipe_crc-DEBUG: crc for vblank 698273, target
> 698278; crc[0]=b82b36e4
> (kms_flip_tiling:14145) igt_pipe_crc-DEBUG: crc for vblank 698274, target
> 698278; crc[0]=b82b36e4
> (kms_flip_tiling:14145) igt_pipe_crc-DEBUG: crc for vblank 698275, target
> 698278; crc[0]=b82b36e4
> (kms_flip_tiling:14145) igt_pipe_crc-DEBUG: crc for vblank 698276, target
> 698278; crc[0]=b82b36e4
> (kms_flip_tiling:14145) igt_pipe_crc-DEBUG: crc for vblank 698277, target
> 698278; crc[0]=b82b36e4
> (kms_flip_tiling:14145) igt_pipe_crc-DEBUG: crc for vblank 698278, target
> 698278; crc[0]=7b978b62
> 
> reference_crc[0]=7b978b62
> 
> Compare after flip:
> ------------------------------------------
> (kms_flip_tiling:14145) igt_pipe_crc-DEBUG: crc for vblank 698279, target
> 698281; crc[0]=dbec96bd
> (kms_flip_tiling:14145) igt_pipe_crc-DEBUG: crc for vblank 698280, target
> 698281; crc[0]=da444d0a
> (kms_flip_tiling:14145) igt_pipe_crc-DEBUG: crc for vblank 698281, target
> 698281; crc[0]=b82b36e4
> 
> reference_crc[0]=7b978b62 crc[0]=b82b36e4

This is pretty interesting.

b82b36e4 (vblank 698273 to 698277) = b82b36e4 (vblank 698281)

But the vblank 698278 came before the page flip, so, why was that different?
It doesn't look reliable. Should we then get a few samples and stick with
the most seen one? :(


> 
> (kms_flip_tiling:14145) igt_pipe_crc-DEBUG: CRC mismatch at index 0:
> 0x7b978b62 != 0xb82b36e4
> 
> Second thing - how come xe shards have ADL-P when xe does not support it,
> while i915 shards don't, when it does? :))
> 
> Regards,
> 
> Tvrtko