[PATCH 1/2] drm/xe: move page fault descriptors to uc types file
Dafna Hirschfeld
dafna.hirschfeld at intel.com
Sun Feb 9 12:12:16 UTC 2025
Future asic will have different firmware to handle page faults.
Meanwhile future asic will have the same pf descriptor as guc
so we should move the descriptors to xe_uc_fw_types.c
Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld at intel.com>
---
drivers/gpu/drm/xe/xe_gt_pagefault.c | 14 ++---
drivers/gpu/drm/xe/xe_guc_fwif.h | 82 ---------------------------
drivers/gpu/drm/xe/xe_uc_fw_types.h | 83 ++++++++++++++++++++++++++++
3 files changed, 90 insertions(+), 89 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_gt_pagefault.c b/drivers/gpu/drm/xe/xe_gt_pagefault.c
index d331a8d02975..7a103e7cd3d0 100644
--- a/drivers/gpu/drm/xe/xe_gt_pagefault.c
+++ b/drivers/gpu/drm/xe/xe_gt_pagefault.c
@@ -251,7 +251,7 @@ static int handle_pagefault(struct xe_gt *gt, struct pagefault *pf)
}
static int send_pagefault_reply(struct xe_guc *guc,
- struct xe_guc_pagefault_reply *reply)
+ struct xe_uc_pagefault_reply *reply)
{
u32 action[] = {
XE_GUC_ACTION_PAGE_FAULT_RES_DESC,
@@ -284,12 +284,12 @@ static void print_pagefault(struct xe_device *xe, struct pagefault *pf)
static bool get_pagefault(struct pf_queue *pf_queue, struct pagefault *pf)
{
- const struct xe_guc_pagefault_desc *desc;
+ const struct xe_uc_pagefault_desc *desc;
bool ret = false;
spin_lock_irq(&pf_queue->lock);
if (pf_queue->tail != pf_queue->head) {
- desc = (const struct xe_guc_pagefault_desc *)
+ desc = (const struct xe_uc_pagefault_desc *)
(pf_queue->data + pf_queue->tail);
pf->fault_level = FIELD_GET(PFD_FAULT_LEVEL, desc->dw0);
@@ -369,7 +369,7 @@ static void pf_queue_work_func(struct work_struct *w)
struct pf_queue *pf_queue = container_of(w, struct pf_queue, worker);
struct xe_gt *gt = pf_queue->gt;
struct xe_device *xe = gt_to_xe(gt);
- struct xe_guc_pagefault_reply reply = {};
+ struct xe_uc_pagefault_reply reply = {};
struct pagefault pf = {};
unsigned long threshold;
int ret;
@@ -395,7 +395,7 @@ static void pf_queue_work_func(struct work_struct *w)
reply.dw0 = FIELD_PREP(PFR_VALID, 1) |
FIELD_PREP(PFR_SUCCESS, pf.fault_unsuccessful) |
- FIELD_PREP(PFR_REPLY, PFR_ACCESS) |
+ FIELD_PREP(PFR_REPLY, PFR_TYPE_ACCESS) |
FIELD_PREP(PFR_DESC_TYPE, FAULT_RESPONSE_DESC) |
FIELD_PREP(PFR_ASID, pf.asid);
@@ -617,12 +617,12 @@ static int handle_acc(struct xe_gt *gt, struct acc *acc)
static bool get_acc(struct acc_queue *acc_queue, struct acc *acc)
{
- const struct xe_guc_acc_desc *desc;
+ const struct xe_uc_acc_desc *desc;
bool ret = false;
spin_lock(&acc_queue->lock);
if (acc_queue->tail != acc_queue->head) {
- desc = (const struct xe_guc_acc_desc *)
+ desc = (const struct xe_uc_acc_desc *)
(acc_queue->data + acc_queue->tail);
acc->granularity = FIELD_GET(ACC_GRANULARITY, desc->dw2);
diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
index f4ec8428ef64..0678375e8ced 100644
--- a/drivers/gpu/drm/xe/xe_guc_fwif.h
+++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
@@ -266,91 +266,9 @@ struct guc_um_init_params {
struct guc_um_queue_params queue_params[GUC_UM_HW_QUEUE_MAX];
} __packed;
-enum xe_guc_fault_reply_type {
- PFR_ACCESS = 0,
- PFR_ENGINE,
- PFR_VFID,
- PFR_ALL,
- PFR_INVALID
-};
-
enum xe_guc_response_desc_type {
TLB_INVALIDATION_DESC = 0,
FAULT_RESPONSE_DESC
};
-struct xe_guc_pagefault_desc {
- u32 dw0;
-#define PFD_FAULT_LEVEL GENMASK(2, 0)
-#define PFD_SRC_ID GENMASK(10, 3)
-#define PFD_RSVD_0 GENMASK(17, 11)
-#define XE2_PFD_TRVA_FAULT BIT(18)
-#define PFD_ENG_INSTANCE GENMASK(24, 19)
-#define PFD_ENG_CLASS GENMASK(27, 25)
-#define PFD_PDATA_LO GENMASK(31, 28)
-
- u32 dw1;
-#define PFD_PDATA_HI GENMASK(11, 0)
-#define PFD_PDATA_HI_SHIFT 4
-#define PFD_ASID GENMASK(31, 12)
-
- u32 dw2;
-#define PFD_ACCESS_TYPE GENMASK(1, 0)
-#define PFD_FAULT_TYPE GENMASK(3, 2)
-#define PFD_VFID GENMASK(9, 4)
-#define PFD_RSVD_1 BIT(10)
-#define XE3P_PFD_PREFETCH BIT(11)
-#define PFD_VIRTUAL_ADDR_LO GENMASK(31, 12)
-#define PFD_VIRTUAL_ADDR_LO_SHIFT 12
-
- u32 dw3;
-#define PFD_VIRTUAL_ADDR_HI GENMASK(31, 0)
-#define PFD_VIRTUAL_ADDR_HI_SHIFT 32
-} __packed;
-
-struct xe_guc_pagefault_reply {
- u32 dw0;
-#define PFR_VALID BIT(0)
-#define PFR_SUCCESS BIT(1)
-#define PFR_REPLY GENMASK(4, 2)
-#define PFR_RSVD_0 GENMASK(9, 5)
-#define PFR_DESC_TYPE GENMASK(11, 10)
-#define PFR_ASID GENMASK(31, 12)
-
- u32 dw1;
-#define PFR_VFID GENMASK(5, 0)
-#define XE3P_PFR_PREFETCH BIT(6)
-#define PFR_ENG_INSTANCE GENMASK(12, 7)
-#define PFR_ENG_CLASS GENMASK(15, 13)
-#define PFR_PDATA GENMASK(31, 16)
-
- u32 dw2;
-#define PFR_RSVD_2 GENMASK(31, 0)
-} __packed;
-
-struct xe_guc_acc_desc {
- u32 dw0;
-#define ACC_TYPE BIT(0)
-#define ACC_TRIGGER 0
-#define ACC_NOTIFY 1
-#define ACC_SUBG_LO GENMASK(31, 1)
-
- u32 dw1;
-#define ACC_SUBG_HI BIT(0)
-#define ACC_RSVD0 GENMASK(2, 1)
-#define ACC_ENG_INSTANCE GENMASK(8, 3)
-#define ACC_ENG_CLASS GENMASK(11, 9)
-#define ACC_ASID GENMASK(31, 12)
-
- u32 dw2;
-#define ACC_VFID GENMASK(5, 0)
-#define ACC_RSVD1 GENMASK(7, 6)
-#define ACC_GRANULARITY GENMASK(10, 8)
-#define ACC_RSVD2 GENMASK(16, 11)
-#define ACC_VIRTUAL_ADDR_RANGE_LO GENMASK(31, 17)
-
- u32 dw3;
-#define ACC_VIRTUAL_ADDR_RANGE_HI GENMASK(31, 0)
-} __packed;
-
#endif
diff --git a/drivers/gpu/drm/xe/xe_uc_fw_types.h b/drivers/gpu/drm/xe/xe_uc_fw_types.h
index 90a451d03518..0755d0b61227 100644
--- a/drivers/gpu/drm/xe/xe_uc_fw_types.h
+++ b/drivers/gpu/drm/xe/xe_uc_fw_types.h
@@ -81,6 +81,89 @@ enum xe_uc_fw_version_types {
XE_UC_FW_VER_TYPE_COUNT
};
+/* currently only guc uses this */
+struct xe_uc_pagefault_reply {
+ u32 dw0;
+#define PFR_VALID BIT(0)
+#define PFR_SUCCESS BIT(1)
+#define PFR_REPLY GENMASK(4, 2)
+#define PFR_RSVD_0 GENMASK(9, 5)
+#define PFR_DESC_TYPE GENMASK(11, 10)
+#define PFR_ASID GENMASK(31, 12)
+
+ u32 dw1;
+#define PFR_VFID GENMASK(5, 0)
+#define XE3P_PFR_PREFETCH BIT(6)
+#define PFR_ENG_INSTANCE GENMASK(12, 7)
+#define PFR_ENG_CLASS GENMASK(15, 13)
+#define PFR_PDATA GENMASK(31, 16)
+
+ u32 dw2;
+#define PFR_RSVD_2 GENMASK(31, 0)
+} __packed;
+
+struct xe_uc_pagefault_desc {
+ u32 dw0;
+#define PFD_FAULT_LEVEL GENMASK(2, 0)
+#define PFD_SRC_ID GENMASK(10, 3)
+#define PFD_RSVD_0 GENMASK(17, 11)
+#define XE2_PFD_TRVA_FAULT BIT(18)
+#define PFD_ENG_INSTANCE GENMASK(24, 19)
+#define PFD_ENG_CLASS GENMASK(27, 25)
+#define PFD_PDATA_LO GENMASK(31, 28)
+
+ u32 dw1;
+#define PFD_PDATA_HI GENMASK(11, 0)
+#define PFD_PDATA_HI_SHIFT 4
+#define PFD_ASID GENMASK(31, 12)
+
+ u32 dw2;
+#define PFD_ACCESS_TYPE GENMASK(1, 0)
+#define PFD_FAULT_TYPE GENMASK(3, 2)
+#define PFD_VFID GENMASK(9, 4)
+#define PFD_RSVD_1 BIT(10)
+#define XE3P_PFD_PREFETCH BIT(11)
+#define PFD_VIRTUAL_ADDR_LO GENMASK(31, 12)
+#define PFD_VIRTUAL_ADDR_LO_SHIFT 12
+
+ u32 dw3;
+#define PFD_VIRTUAL_ADDR_HI GENMASK(31, 0)
+#define PFD_VIRTUAL_ADDR_HI_SHIFT 32
+} __packed;
+
+struct xe_uc_acc_desc {
+ u32 dw0;
+#define ACC_TYPE BIT(0)
+#define ACC_TRIGGER 0
+#define ACC_NOTIFY 1
+#define ACC_SUBG_LO GENMASK(31, 1)
+
+ u32 dw1;
+#define ACC_SUBG_HI BIT(0)
+#define ACC_RSVD0 GENMASK(2, 1)
+#define ACC_ENG_INSTANCE GENMASK(8, 3)
+#define ACC_ENG_CLASS GENMASK(11, 9)
+#define ACC_ASID GENMASK(31, 12)
+
+ u32 dw2;
+#define ACC_VFID GENMASK(5, 0)
+#define ACC_RSVD1 GENMASK(7, 6)
+#define ACC_GRANULARITY GENMASK(10, 8)
+#define ACC_RSVD2 GENMASK(16, 11)
+#define ACC_VIRTUAL_ADDR_RANGE_LO GENMASK(31, 17)
+
+ u32 dw3;
+#define ACC_VIRTUAL_ADDR_RANGE_HI GENMASK(31, 0)
+} __packed;
+
+enum xe_uc_fault_reply_type {
+ PFR_TYPE_ACCESS = 0,
+ PFR_TYPE_ENGINE,
+ PFR_TYPE_VFID,
+ PFR_TYPE_ALL,
+ PFR_TYPE_INVALID
+};
+
/**
* struct xe_uc_fw - XE micro controller firmware
*/
--
2.34.1
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