[PATCH 14/17] drm/i915/ddi: Reuse helper to compute the HDMI DDI_BUF_CTL config

[Kahola, Mika]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Imre
> Deak
> Sent: Wednesday, 29 January 2025 22.02
> To: intel-gfx at lists.freedesktop.org; intel-xe at lists.freedesktop.org
> Subject: [PATCH 14/17] drm/i915/ddi: Reuse helper to compute the HDMI
> DDI_BUF_CTL config
> 
> Reuse the existing helper to compute the configuration value of the DDI_BUF_CTL
> register for HDMI outputs instead of open-coding this.
> 
> Note that dropping the XE2LPD_DDI_BUF_D2D_LINK_ENABLE flag is ok, since an
> earlier mtl_ddi_enable_d2d() has set it already and intel_enable_ddi_buf()'s
> RMW will not update this flag.
> 

Reviewed-by: Mika Kahola <mika.kahola at intel.com>

> Signed-off-by: Imre Deak <imre.deak at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 30 ++++++++----------------
>  1 file changed, 10 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index dd8ae5cf96c70..e03ec9a235d33 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -339,11 +339,14 @@ static u32 intel_ddi_buf_ctl_config_val(struct
> intel_encoder *encoder,
>  	struct intel_display *display = to_intel_display(encoder);
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +	bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
>  	u32 val = 0;
> 
>  	/* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain()
> later */
> -	val |= DDI_PORT_WIDTH(crtc_state->lane_count) |
> -		DDI_BUF_TRANS_SELECT(0);
> +	if (is_dp || DISPLAY_VER(display) >= 14)
> +		val |= DDI_PORT_WIDTH(crtc_state->lane_count);
> +
> +	val |= DDI_BUF_TRANS_SELECT(0);
> 
>  	if (dig_port->lane_reversal)
>  		val |= DDI_BUF_PORT_REVERSAL;
> @@ -351,14 +354,15 @@ static u32 intel_ddi_buf_ctl_config_val(struct
> intel_encoder *encoder,
>  		val |= DDI_A_4_LANES;
> 
>  	if (DISPLAY_VER(i915) >= 14) {
> -		if (intel_dp_is_uhbr(crtc_state))
> +		if (is_dp && intel_dp_is_uhbr(crtc_state))
>  			val |= DDI_BUF_PORT_DATA_40BIT;
>  		else
>  			val |= DDI_BUF_PORT_DATA_10BIT;
>  	}
> 
>  	if (IS_ALDERLAKE_P(i915) && intel_encoder_is_tc(encoder)) {
> -		val |= ddi_buf_phy_link_rate(crtc_state->port_clock);
> +		if (is_dp)
> +			val |= ddi_buf_phy_link_rate(crtc_state->port_clock);
>  		/*
>  		 * TODO: remove the following once DDI_BUF_CTL is updated
> via
>  		 * an RMW everywhere.
> @@ -367,7 +371,7 @@ static u32 intel_ddi_buf_ctl_config_val(struct
> intel_encoder *encoder,
>  			val |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
>  	}
> 
> -	if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) {
> +	if (is_dp && IS_DISPLAY_VER(display, 11, 13) &&
> +intel_encoder_is_tc(encoder)) {
>  		int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock);
> 
>  		val |= DDI_BUF_LANE_STAGGER_DELAY(delay);
> @@ -3417,7 +3421,6 @@ static void intel_ddi_enable_hdmi(struct
> intel_atomic_state *state,
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	struct drm_connector *connector = conn_state->connector;
>  	enum port port = encoder->port;
> -	u32 buf_ctl = 0;
> 
>  	if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
>  					       crtc_state-
> >hdmi_high_tmds_clock_ratio,
> @@ -3482,11 +3485,6 @@ static void intel_ddi_enable_hdmi(struct
> intel_atomic_state *state,
>  	 * is filled with lane count, already set in the crtc_state.
>  	 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
>  	 */
> -	if (dig_port->lane_reversal)
> -		buf_ctl |= DDI_BUF_PORT_REVERSAL;
> -	if (dig_port->ddi_a_4_lanes)
> -		buf_ctl |= DDI_A_4_LANES;
> -
>  	if (DISPLAY_VER(dev_priv) >= 14) {
>  		u32 port_buf = 0;
> 
> @@ -3497,17 +3495,9 @@ static void intel_ddi_enable_hdmi(struct
> intel_atomic_state *state,
> 
>  		intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv,
> port),
>  			     XELPDP_PORT_WIDTH_MASK |
> XELPDP_PORT_REVERSAL, port_buf);
> -
> -		buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count);
> -
> -		if (DISPLAY_VER(dev_priv) >= 20)
> -			buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> -	} else if (IS_ALDERLAKE_P(dev_priv) && intel_encoder_is_tc(encoder)) {
> -		drm_WARN_ON(&dev_priv->drm,
> !intel_tc_port_in_legacy_mode(dig_port));
> -		buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
>  	}
> 
> -	intel_enable_ddi_buf(encoder, buf_ctl);
> +	intel_enable_ddi_buf(encoder, intel_ddi_buf_ctl_config_val(encoder,
> +crtc_state));
>  }
> 
>  static void intel_ddi_enable(struct intel_atomic_state *state,
> --
> 2.44.2