[PATCH v2] drm/i915/display: implement wa_18038517565

[Jani Nikula]

On Tue, 11 Feb 2025, Vinod Govindapillai <vinod.govindapillai at intel.com> wrote:
> Disable FBC compressor clock gating before enabling FBC and
> clear it after disabling FBC.
>
> v2: update the DG2 registers for this wa
>
> Bspec: 74212, 72197, 69741, 65555
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c | 23 +++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h          |  7 +++++++
>  2 files changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index df05904bac8a..ac11110159f1 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -522,6 +522,21 @@ static void ilk_fbc_activate(struct intel_fbc *fbc)
>  		       DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
>  }
>  
> +static void fbc_compressor_clkgate_disable_wa(struct intel_fbc *fbc,
> +					      bool disable)
> +{
> +	struct intel_display *display = fbc->display;
> +
> +	if (display->platform.dg2)
> +		intel_de_rmw(fbc->display, GEN9_CLKGATE_DIS_4,

You already have display local variable, use it.

> +			     DG2_DPFC_GATING_DIS,
> +			     disable ? DG2_DPFC_GATING_DIS : 0);
> +	else if (DISPLAY_VER(display) >= 14)
> +		intel_de_rmw(fbc->display, MTL_PIPE_CLKGATE_DIS2(fbc->id),

Ditto.

> +			     MTL_DPFC_GATING_DIS,
> +			     disable ? MTL_DPFC_GATING_DIS : 0);
> +}
> +
>  static void ilk_fbc_deactivate(struct intel_fbc *fbc)
>  {
>  	struct intel_display *display = fbc->display;
> @@ -532,6 +547,10 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc)
>  	if (dpfc_ctl & DPFC_CTL_EN) {
>  		dpfc_ctl &= ~DPFC_CTL_EN;
>  		intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
> +
> +		/* wa_18038517565 Enable DPFC clock gating after FBC disable */
> +		if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
> +			fbc_compressor_clkgate_disable_wa(fbc, false);
>  	}
>  }
>  
> @@ -912,6 +931,10 @@ static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
>  	if (DISPLAY_VER(display) >= 11 && !IS_DG2(i915))
>  		intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id),
>  			     0, DPFC_CHICKEN_FORCE_SLB_INVALIDATION);
> +
> +	/* wa_18038517565 Disable DPFC clock gating before FBC enable */
> +	if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
> +		fbc_compressor_clkgate_disable_wa(fbc, true);
>  }
>  
>  static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 670cd2371f94..6a95bf472258 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1043,6 +1043,7 @@
>  
>  #define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)
>  #define   BXT_GMBUS_GATING_DIS		(1 << 14)
> +#define   DG2_DPFC_GATING_DIS		REG_BIT(31)
>  
>  #define GEN9_CLKGATE_DIS_5		_MMIO(0x46540)
>  #define   DPCE_GATING_DIS		REG_BIT(17)
> @@ -4273,6 +4274,12 @@ enum skl_power_gate {
>  #define MTL_CLKGATE_DIS_TRANS(dev_priv, trans)			_MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A)
>  #define  MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS		REG_BIT(7)
>  
> +#define _MTL_PIPE_CLKGATE_DIS2_A			0x60114
> +#define _MTL_PIPE_CLKGATE_DIS2_B			0x61114
> +#define MTL_PIPE_CLKGATE_DIS2(pipe) \
> +	_MMIO_PIPE(pipe, _MTL_PIPE_CLKGATE_DIS2_A, _MTL_PIPE_CLKGATE_DIS2_B)

In the register definitions, please err towards longer lines.

> +#define   MTL_DPFC_GATING_DIS			REG_BIT(6)
> +
>  #define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
>  #define   MTL_N_OF_ENABLED_QGV_POINTS_MASK	REG_GENMASK(11, 8)
>  #define   MTL_N_OF_POPULATED_CH_MASK		REG_GENMASK(7, 4)

-- 
Jani Nikula, Intel