[PATCH 17/17] drm/i915/ddi: Unify the platform specific functions enabling a port

[Kahola, Mika]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces at lists.freedesktop.org> On Behalf Of Imre Deak
> Sent: Wednesday, 29 January 2025 22.02
> To: intel-gfx at lists.freedesktop.org; intel-xe at lists.freedesktop.org
> Subject: [PATCH 17/17] drm/i915/ddi: Unify the platform specific functions
> enabling a port
> 
> The functions enabling a port (as part of link training) for MTL+ and earlier
> platforms only differ by extra steps on MTL+:
> - enable the D2D link
> - set the link parameters
> - configure the PORT_BUF_CTL1 register
> 
> and an extra step on earlier platforms:
> - apply an ADLP TypeC workaround
> 
> All the extra steps are already/can be skipped on unrelated platforms.
> Combine the two functions accounting for the above differences, removing the
> duplication.
> 

Reviewed-by: Mika Kahola <mika.kahola at intel.com>

> Signed-off-by: Imre Deak <imre.deak at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 52 ++++--------------------
>  1 file changed, 8 insertions(+), 44 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a2d82a4c4aa77..e8bea49a27dbc 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2721,7 +2721,7 @@ static void mtl_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
>  	 * stream or multi-stream master transcoder" can just be performed
>  	 * unconditionally here.
>  	 *
> -	 * mtl_ddi_prepare_link_retrain() that is called by
> +	 * intel_ddi_prepare_link_retrain() that is called by
>  	 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h,
>  	 * 6.i and 6.j
>  	 *
> @@ -3713,8 +3713,8 @@ static void adlp_tbt_to_dp_alt_switch_wa(struct
> intel_encoder *encoder)
>  		intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln),
> DKL_PCS_DW5_CORE_SOFTRESET, 0);  }
> 
> -static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
> -					 const struct intel_crtc_state
> *crtc_state)
> +static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
> +					   const struct intel_crtc_state
> *crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); @@ -
> 3729,7 +3729,6 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp
> *intel_dp,
> 
>  	drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE);
> 
> -	/* 6.d Configure and enable DP_TP_CTL with link training pattern 1
> selected */
>  	dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
>  	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) ||
>  	    intel_dp_is_uhbr(crtc_state)) {
> @@ -3742,16 +3741,15 @@ static void mtl_ddi_prepare_link_retrain(struct
> intel_dp *intel_dp,
>  	intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
>  	intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));
> 
> -	/* 6.f Enable D2D Link */
> +	adlp_tbt_to_dp_alt_switch_wa(encoder);
> +
>  	mtl_ddi_enable_d2d(encoder);
> 
> -	/* 6.g Configure voltage swing and related IO settings */
> -	encoder->set_signal_levels(encoder, crtc_state);
> +	if (DISPLAY_VER(display) >= 14)
> +		encoder->set_signal_levels(encoder, crtc_state);
> 
> -	/* 6.h Configure PORT_BUF_CTL1 */
>  	mtl_port_buf_ctl_program(encoder, crtc_state);
> 
> -	/* 6.i Configure and enable DDI_CTL_DE to start sending valid data to
> port slice */
>  	if (DISPLAY_VER(display) >= 20)
>  		intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> 
> @@ -3759,36 +3757,6 @@ static void mtl_ddi_prepare_link_retrain(struct
> intel_dp *intel_dp,
>  	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
>  }
> 
> -static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
> -					   const struct intel_crtc_state
> *crtc_state)
> -{
> -	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> -	struct intel_encoder *encoder = &dig_port->base;
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	u32 dp_tp_ctl;
> -
> -	dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
> -
> -	drm_WARN_ON(&dev_priv->drm, dp_tp_ctl & DP_TP_CTL_ENABLE);
> -
> -	dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
> -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) ||
> -	    intel_dp_is_uhbr(crtc_state)) {
> -		dp_tp_ctl |= DP_TP_CTL_MODE_MST;
> -	} else {
> -		dp_tp_ctl |= DP_TP_CTL_MODE_SST;
> -		if (crtc_state->enhanced_framing)
> -			dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
> -	}
> -	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
> -	intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
> -
> -	adlp_tbt_to_dp_alt_switch_wa(encoder);
> -
> -	intel_enable_ddi_buf(encoder, intel_dp->DP);
> -	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
> -}
> -
>  static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
>  				     const struct intel_crtc_state *crtc_state,
>  				     u8 dp_train_pat)
> @@ -4612,7 +4580,6 @@ static const struct drm_encoder_funcs intel_ddi_funcs
> = {
> 
>  static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)  {
> -	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>  	struct intel_connector *connector;
>  	enum port port = dig_port->base.port;
> 
> @@ -4621,10 +4588,7 @@ static int intel_ddi_init_dp_connector(struct
> intel_digital_port *dig_port)
>  		return -ENOMEM;
> 
>  	dig_port->dp.output_reg = DDI_BUF_CTL(port);
> -	if (DISPLAY_VER(i915) >= 14)
> -		dig_port->dp.prepare_link_retrain =
> mtl_ddi_prepare_link_retrain;
> -	else
> -		dig_port->dp.prepare_link_retrain =
> intel_ddi_prepare_link_retrain;
> +	dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
>  	dig_port->dp.set_link_train = intel_ddi_set_link_train;
>  	dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
> 
> --
> 2.44.2