✗ CI.checkpatch: warning for drm/i915/display: Allow display PHYs to reset power state (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Allow display PHYs to reset power state (rev3)
URL   : https://patchwork.freedesktop.org/series/144103/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
22f9cda3436b4fe965b5c5f31d2f2c1bcb483189
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 86066a284de8b49fce18a1472ac8867429a4e73c
Author: Mika Kahola <mika.kahola at intel.com>
Date:   Fri Feb 14 16:04:42 2025 +0200

    drm/i915/display: Allow display PHYs to reset power state
    
    The dedicated display PHYs reset to a power state that blocks S0ix,
    increasing idle system power. After a system reset (cold boot,
    S3/4/5, warm reset) if a dedicated PHY is not being brought up
    shortly, use these steps to move the PHY to the lowest power state
    to save power.
    
    1. Follow the PLL Enable Sequence, using any valid frequency such as DP 1.62 GHz.
       This brings lanes out of reset and enables the PLL to allow powerdown to be moved
       to the Disable state.
    2. Follow PLL Disable Sequence. This moves powerdown to the Disable state and disables the PLL.
    
    v2: Rename WA function to more descriptive (Jani)
        For PTL, only port A needs this wa
        Add helpers to check presence of C10 phy and pll enabling (Imre)
    v3: Rename wa function (Imre)
        Check return value of C10 pll tables readout (Imre)
        Use PLL request to check pll enabling (Imre)
    
    Signed-off-by: Mika Kahola <mika.kahola at intel.com>
+ /mt/dim checkpatch 57457d93f156d8b4bdff8d138127d81b8f97d8c9 drm-intel
302ea8dca81b drm/i915/display: Drop crtc_state from C10/C20 pll programming
-:60: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#60: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2052:
+					      const struct intel_c10pll_state * const *tables, int port_clock, bool is_dp,

-:256: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#256: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:3093:
+			      intel_crtc_has_dp_encoder(crtc_state), crtc_state->port_clock, crtc_state->lane_count);

-:258: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#258: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:3095:
+
+}

total: 0 errors, 2 warnings, 1 checks, 226 lines checked
86066a284de8 drm/i915/display: Allow display PHYs to reset power state
-:12: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#12: 
1. Follow the PLL Enable Sequence, using any valid frequency such as DP 1.62 GHz.

-:38: ERROR:CODE_INDENT: code indent should use tabs where possible
#38: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:3566:
+        struct intel_digital_port *dig_port = enc_to_dig_port(encoder);$

-:38: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#38: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:3566:
+        struct intel_digital_port *dig_port = enc_to_dig_port(encoder);$

total: 1 errors, 2 warnings, 0 checks, 89 lines checked