[PATCH v4 1/2] drm/xe: Add Wa_16021333562 and Wa_14016712196

[Lucas De Marchi]

+Daniele


On Thu, Jan 30, 2025 at 05:59:38AM +0000, Aradhya Bhatia wrote:
>Wa_16021333562 and Wa_14016712196 are permanent workarounds that apply
>to multiple platforms. Wa_16021333562 applies to platforms ranging from
>TGL (12.00) to Xe_LPM (13.00), while Wa_14016712196 from DG2 (12.55) to
>Xe_LPG (12.74).
>
>Signed-off-by: Aradhya Bhatia <aradhya.bhatia at intel.com>
>---
> drivers/gpu/drm/xe/xe_guc_ads.c    | 2 +-
> drivers/gpu/drm/xe/xe_ring_ops.c   | 4 ++++
> drivers/gpu/drm/xe/xe_wa_oob.rules | 4 ++++
> 3 files changed, 9 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
>index fab259adc380..e7c9e095a19f 100644
>--- a/drivers/gpu/drm/xe/xe_guc_ads.c
>+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
>@@ -342,7 +342,7 @@ static void guc_waklv_init(struct xe_guc_ads *ads)
> 	offset = guc_ads_waklv_offset(ads);
> 	remain = guc_ads_waklv_size(ads);
>
>-	if (XE_WA(gt, 14019882105))
>+	if (XE_WA(gt, 14019882105) || XE_WA(gt, 16021333562))
> 		guc_waklv_enable_simple(ads,
> 					GUC_WORKAROUND_KLV_BLOCK_INTERRUPTS_WHEN_MGSR_BLOCKED,
> 					&offset, &remain);
>diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
>index 9f327f27c072..29cd7b548493 100644
>--- a/drivers/gpu/drm/xe/xe_ring_ops.c
>+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
>@@ -192,6 +192,10 @@ static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i)
> 	else if (job->q->class == XE_ENGINE_CLASS_COMPUTE)
> 		flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
>
>+	if (XE_WA(gt, 14016712196))
>+		i = emit_pipe_control(dw, i, 0, PIPE_CONTROL_DEPTH_CACHE_FLUSH,
>+				      LRC_PPHWSP_SCRATCH_ADDR, 0);

this has a build time conflict with commit f0c06677d110 ("drm/xe/pxp:
Add VCS inline termination support"). AFAICS it should be renamed to
LRC_PPHWSP_FLUSH_INVAL_SCRATCH_ADDR, right?

Looking at the impl, it seems we should also move it earlier, so:

diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index eec623ed0f562..839a19aa46f46 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -177,6 +177,10 @@ static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i)
         bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK);
         u32 flags;
  
+       if (XE_WA(gt, 14016712196))
+               i = emit_pipe_control(dw, i, 0, PIPE_CONTROL_DEPTH_CACHE_FLUSH,
+                                     LRC_PPHWSP_FLUSH_INVAL_SCRATCH_ADDR, 0);
+
         flags = (PIPE_CONTROL_CS_STALL |
                  PIPE_CONTROL_TILE_CACHE_FLUSH |
                  PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
@@ -192,10 +196,6 @@ static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i)
         else if (job->q->class == XE_ENGINE_CLASS_COMPUTE)
                 flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
  
-       if (XE_WA(gt, 14016712196))
-               i = emit_pipe_control(dw, i, 0, PIPE_CONTROL_DEPTH_CACHE_FLUSH,
-                                     LRC_PPHWSP_SCRATCH_ADDR, 0);
-
         return emit_pipe_control(dw, i, PIPE_CONTROL0_HDC_PIPELINE_FLUSH, flags, 0, 0);
  }


because of the rename and all the other flags and calculations are about the last
emit_pipe_control(), not this one we are adding.

Lucas De Marchi

>+
> 	return emit_pipe_control(dw, i, PIPE_CONTROL0_HDC_PIPELINE_FLUSH, flags, 0, 0);
> }
>
>diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
>index 228436532282..ea72bcc02e1e 100644
>--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
>+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
>@@ -43,3 +43,7 @@
> no_media_l3	MEDIA_VERSION(3000)
> 14022866841	GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)
> 		MEDIA_VERSION(3000), MEDIA_STEP(A0, B0)
>+16021333562	GRAPHICS_VERSION_RANGE(1200, 1274)
>+		MEDIA_VERSION(1300)
>+14016712196	GRAPHICS_VERSION(1255)
>+		GRAPHICS_VERSION_RANGE(1270, 1274)
>-- 
>2.45.2
>