✗ CI.checkpatch: warning for perf/x86/rapl: Fix PP1 event for Intel Meteor/Lunar Lake

[Patchwork]

== Series Details ==

Series: perf/x86/rapl: Fix PP1 event for Intel Meteor/Lunar Lake
URL   : https://patchwork.freedesktop.org/series/145183/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
22f9cda3436b4fe965b5c5f31d2f2c1bcb483189
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 98b61a535c00820e1699e18a8f0dd9ec25a39931
Author: Lucas De Marchi <lucas.demarchi at intel.com>
Date:   Thu Feb 20 07:36:30 2025 -0800

    perf/x86/rapl: Fix PP1 event for Intel Meteor/Lunar Lake
    
    On some boots the read of MSR_PP1_ENERGY_STATUS msr returns 0, causing
    perf_msr_probe() to make the power/events/energy-gpu event non-visible.
    When that happens, the msr always read 0 until the graphics module (i915
    for Meteor Lake, xe for Lunar Lake) is loaded. Then it starts returning
    something different and re-loading the rapl module "fixes" it.
    
    This is tested on the following platforms with the fail rates before
    this patch:
    
            Alder Lake S    0/20
            Arrow Lake H    0/20
            Lunar Lake M    8/20
            Meteor Lake U   6/20
            Raptor Lake P   4/20
            Raptor Lake S   0/20
    
    For those platforms failing, use a separate msr list with .no_check
    set so it doesn't check the runtime value to create the event - it will
    just return 0 until the i915/xe module initializes the GPU.
    
    The issue https://github.com/ulissesf/qmassa/issues/4 is workarounded by
    reading the MSR directly since it works after xe is loaded, but the
    issue with not having the perf event is still there.
    
    Closes: https://github.com/ulissesf/qmassa/issues/4
    Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/4241
    Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com
+ /mt/dim checkpatch 8554d5b7b4fded481a85ab11d75eeb97443450e2 drm-intel
98b61a535c00 perf/x86/rapl: Fix PP1 event for Intel Meteor/Lunar Lake
-:32: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Lucas De Marchi <lucas.demarchi at intel.com'
#32: 
Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com

-:43: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#43: FILE: arch/x86/events/rapl.c:592:
+	[PERF_RAPL_PP0]  = { MSR_PP0_ENERGY_STATUS,      &rapl_events_cores_group, test_msr, false, RAPL_MSR_MASK },

-:44: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#44: FILE: arch/x86/events/rapl.c:593:
+	[PERF_RAPL_PKG]  = { MSR_PKG_ENERGY_STATUS,      &rapl_events_pkg_group,   test_msr, false, RAPL_MSR_MASK },

-:45: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#45: FILE: arch/x86/events/rapl.c:594:
+	[PERF_RAPL_RAM]  = { MSR_DRAM_ENERGY_STATUS,     &rapl_events_ram_group,   test_msr, false, RAPL_MSR_MASK },

-:46: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#46: FILE: arch/x86/events/rapl.c:595:
+	[PERF_RAPL_PP1]  = { MSR_PP1_ENERGY_STATUS,      &rapl_events_gpu_group,   test_msr, true,  RAPL_MSR_MASK },

-:47: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#47: FILE: arch/x86/events/rapl.c:596:
+	[PERF_RAPL_PSYS] = { MSR_PLATFORM_ENERGY_STATUS, &rapl_events_psys_group,  test_msr, false, RAPL_MSR_MASK },

-:87: ERROR:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Lucas De Marchi <lucas.demarchi at intel.com>'

total: 2 errors, 5 warnings, 0 checks, 47 lines checked