[PATCH 3/4] drm/xe/gen12: L3 recommended hashing mask

[Matt Roper]

On Wed, Feb 26, 2025 at 11:21:05AM +0000, Tvrtko Ursulin wrote:
> According to the i915 codebase xe missed to set the recommended
> performance tuning for L3 hashing which is applicable to all legacy XeLP
> platforms. Lets add it.
> 
> v2:
>  * Rename prefixes to XELP_.
>  * Tweak version end point.
> 
> v3:
>  * Add bspec tag.
>  * Tweak version range.
> 
> Bspec: 31870
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at igalia.com>
> References: c46c5fb725be ("drm/i915/gen12: Apply recommended L3 hashing mask")
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 ++++-
>  drivers/gpu/drm/xe/xe_tuning.c       | 6 ++++++
>  2 files changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 282afd22b68b..da833a147c0c 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -365,10 +365,13 @@
>  #define FORCEWAKE_MEDIA_VEBOX(n)		XE_REG(0xa560 + (n) * 4)
>  #define FORCEWAKE_GSC				XE_REG(0xa618)
>  
> +/* L3 Cache Control */
> +#define XELP_GARBCNTL				XE_REG(0xb004)
> +#define   XELP_BUS_HASH_CTL_BIT_EXC		REG_BIT(7)
> +
>  #define XEHPC_LNCFMISCCFGREG0			XE_REG_MCR(0xb01c, XE_REG_OPTION_MASKED)
>  #define   XEHPC_OVRLSCCC			REG_BIT(0)
>  
> -/* L3 Cache Control */
>  #define LNCFCMOCS_REG_COUNT			32
>  #define XELP_LNCFCMOCS(i)			XE_REG(0xb020 + (i) * 4)
>  #define XEHP_LNCFCMOCS(i)			XE_REG_MCR(0xb020 + (i) * 4)
> diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
> index 9e7ec36dbd47..454ee00ef45f 100644
> --- a/drivers/gpu/drm/xe/xe_tuning.c
> +++ b/drivers/gpu/drm/xe/xe_tuning.c
> @@ -107,6 +107,12 @@ static const struct xe_rtp_entry_sr lrc_tunings[] = {

0xb004 isn't part of the LRC (i.e., it doesn't get saved/restored on
context switch), so this isn't the right place to add this.  We'd want
this in engine_tunings[] instead so that the setting gets re-applied by
the GuC following engine resets.


Matt

>  						FF_MODE2_TDS_TIMER_128))
>  	},
>  
> +	{ XE_RTP_NAME("Tuning: L3 Hashing Mask"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210),
> +		       FUNC(xe_rtp_match_first_render_or_compute)),
> +	  XE_RTP_ACTIONS(CLR(XELP_GARBCNTL, XELP_BUS_HASH_CTL_BIT_EXC))
> +	},
> +
>  	/* DG2 */
>  
>  	{ XE_RTP_NAME("Tuning: L3 cache"),
> -- 
> 2.48.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation