[PATCH 4/5] drm/xe/xelp: L3 recommended hashing mask

[Lucas De Marchi]

On Thu, Feb 27, 2025 at 10:13:03AM +0000, Tvrtko Ursulin wrote:
>According to the i915 codebase xe missed to set the recommended
>performance tuning for L3 hashing which is applicable to all legacy XeLP
>platforms. Lets add it.
>
>v2:
> * Rename prefixes to XELP_.
> * Tweak version end point.
>
>v3:
> * Add bspec tag.
> * Tweak version range.
>
>v4:
> * Move from LRC to engine tunings list.
>
>Bspec: 31870
>Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at igalia.com>
>References: c46c5fb725be ("drm/i915/gen12: Apply recommended L3 hashing mask")
>Cc: Lucas De Marchi <lucas.demarchi at intel.com>
>Cc: Matt Roper <matthew.d.roper at intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>


thanks
Lucas De Marchi

>---
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 ++++-
> drivers/gpu/drm/xe/xe_tuning.c       | 5 +++++
> 2 files changed, 9 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>index 282afd22b68b..da833a147c0c 100644
>--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>@@ -365,10 +365,13 @@
> #define FORCEWAKE_MEDIA_VEBOX(n)		XE_REG(0xa560 + (n) * 4)
> #define FORCEWAKE_GSC				XE_REG(0xa618)
>
>+/* L3 Cache Control */
>+#define XELP_GARBCNTL				XE_REG(0xb004)
>+#define   XELP_BUS_HASH_CTL_BIT_EXC		REG_BIT(7)
>+
> #define XEHPC_LNCFMISCCFGREG0			XE_REG_MCR(0xb01c, XE_REG_OPTION_MASKED)
> #define   XEHPC_OVRLSCCC			REG_BIT(0)
>
>-/* L3 Cache Control */
> #define LNCFCMOCS_REG_COUNT			32
> #define XELP_LNCFCMOCS(i)			XE_REG(0xb020 + (i) * 4)
> #define XEHP_LNCFCMOCS(i)			XE_REG_MCR(0xb020 + (i) * 4)
>diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
>index 3c78f3d71559..551c2f308e1c 100644
>--- a/drivers/gpu/drm/xe/xe_tuning.c
>+++ b/drivers/gpu/drm/xe/xe_tuning.c
>@@ -88,6 +88,11 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
> };
>
> static const struct xe_rtp_entry_sr engine_tunings[] = {
>+	{ XE_RTP_NAME("Tuning: L3 Hashing Mask"),
>+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210),
>+		       FUNC(xe_rtp_match_first_render_or_compute)),
>+	  XE_RTP_ACTIONS(CLR(XELP_GARBCNTL, XELP_BUS_HASH_CTL_BIT_EXC))
>+	},
> 	{ XE_RTP_NAME("Tuning: Set Indirect State Override"),
> 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1274),
> 		       ENGINE_CLASS(RENDER)),
>-- 
>2.48.0
>