✗ CI.checkpatch: warning for PSR DSB support (rev2)

[Patchwork]

== Series Details ==

Series: PSR DSB support (rev2)
URL   : https://patchwork.freedesktop.org/series/142521/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit cdafc96e0919300a25b7c9a853b897df7b5fa381
Author: Jouni Högander <jouni.hogander at intel.com>
Date:   Thu Jan 2 10:36:38 2025 +0200

    drm/i915/psr: Allow DSB usage when PSR is enabled
    
    Now as we have correct PSR2_MAN_TRK_CTL handling in place we can allow DSB
    usage also when PSR is enabled for LunarLake onwards.
    
    Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
+ /mt/dim checkpatch 08bd590935a5258ffd79355c59adffd72fb2c642 drm-intel
0daeb5eaaaa9 drm/i915/psr: Use PSR2_MAN_TRK_CTL CFF bit only to send full update
b3a69217a2f7 drm/i915/psr: Rename psr_force_hw_tracking_exit as intel_psr_force_update
68f405b11943 drm/i915/psr: Split setting sff and cff bits away from intel_psr_force_update
f092bf2269f2 drm/i915/psr: Add register definitions for SFF_CTL and CFF_CTL registers
a1fa83a2502a drm/i915/psr: Use SFF_CTL on invalidate/flush for LunarLake onwards
814ffe2acbf0 drm/i915/psr: Allow writing PSR2_MAN_TRK_CTL using DSB
abeacf7f1417 drm/i915/psr: Changes for PSR2_MAN_TRK_CTL handling when DSB is in use
-:17: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#17: 
Taking PSR lock over DSB commit is not needed because PSR2_MAN_TRK_CTL is now

total: 0 errors, 1 warnings, 0 checks, 17 lines checked
1025d61b18d2 drm/i915/psr: Remove DSB_SKIP_WAITS_EN chicken bit
cdafc96e0919 drm/i915/psr: Allow DSB usage when PSR is enabled