✓ CI.checkpatch: success for SSC enablement in port clock programming

[Patchwork]

== Series Details ==

Series: SSC enablement in port clock programming
URL   : https://patchwork.freedesktop.org/series/143128/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit b26878588df02717cab60db18568e689fb07ca70
Author: Suraj Kandpal <suraj.kandpal at intel.com>
Date:   Mon Jan 6 09:38:21 2025 +0530

    drm/i915/cx0: Set ssc_enabled for c20 too
    
    ssc_enabled does not get set for c20 phy legacy native rates.
    This means SSC for MPLLB for legacy rates and UHBR 13.5 is never
    set. This patch makes sure we set ssc_enabled for both c10 and c20.
    
    Signed-off-by: Suraj Kandpal <suraj.kandpal at intel.com>
+ /mt/dim checkpatch 856baaf960db044e0ce5e3f5d04d35a7b9879837 drm-intel
49c3e2d5e877 drm/i915/cx0: Fix SSC enablement in PORT_CLOCK_CTL
b26878588df0 drm/i915/cx0: Set ssc_enabled for c20 too