[PATCH] drm/xe: Introduce the RPa information
Belgaumkar, Vinay
vinay.belgaumkar at intel.com
Wed Jan 8 19:49:25 UTC 2025
On 12/20/2024 7:29 AM, Rodrigo Vivi wrote:
> RPa is the Achievable frequency, defined by PCODE at runtime
> based on multiple running conditions.
This is a good data point in addition to the throttle reasons that can
give insight into pcode's decision process.
Reviewed-by: Vinay Belgaumkar <vinay.belgaumkar at intel.com>
>
> v2: Remove RPA_MASK from i915 file
>
> Cc: Vinay Belgaumkar <vinay.belgaumkar at intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_regs.h | 4 +++
> drivers/gpu/drm/xe/xe_gt_freq.c | 15 ++++++++
> drivers/gpu/drm/xe/xe_guc_pc.c | 53 ++++++++++++++++++++++++++--
> drivers/gpu/drm/xe/xe_guc_pc.h | 1 +
> drivers/gpu/drm/xe/xe_guc_pc_types.h | 2 ++
> 5 files changed, 73 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
> index 3293172b0128..6cf282618836 100644
> --- a/drivers/gpu/drm/xe/regs/xe_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_regs.h
> @@ -44,12 +44,16 @@
>
> #define MTL_RP_STATE_CAP XE_REG(0x138000)
>
> +#define MTL_GT_RPA_FREQUENCY XE_REG(0x138008)
> #define MTL_GT_RPE_FREQUENCY XE_REG(0x13800c)
>
> #define MTL_MEDIAP_STATE_CAP XE_REG(0x138020)
> #define MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
> #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
>
> +#define MTL_MPA_FREQUENCY XE_REG(0x138028)
> +#define MTL_RPA_MASK REG_GENMASK(8, 0)
> +
> #define MTL_MPE_FREQUENCY XE_REG(0x13802c)
> #define MTL_RPE_MASK REG_GENMASK(8, 0)
>
> diff --git a/drivers/gpu/drm/xe/xe_gt_freq.c b/drivers/gpu/drm/xe/xe_gt_freq.c
> index 6bd39b2c5003..604bdc7c8173 100644
> --- a/drivers/gpu/drm/xe/xe_gt_freq.c
> +++ b/drivers/gpu/drm/xe/xe_gt_freq.c
> @@ -115,6 +115,20 @@ static ssize_t rpe_freq_show(struct device *dev,
> }
> static DEVICE_ATTR_RO(rpe_freq);
>
> +static ssize_t rpa_freq_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct xe_guc_pc *pc = dev_to_pc(dev);
> + u32 freq;
> +
> + xe_pm_runtime_get(dev_to_xe(dev));
> + freq = xe_guc_pc_get_rpa_freq(pc);
> + xe_pm_runtime_put(dev_to_xe(dev));
> +
> + return sysfs_emit(buf, "%d\n", freq);
> +}
> +static DEVICE_ATTR_RO(rpa_freq);
> +
> static ssize_t rpn_freq_show(struct device *dev,
> struct device_attribute *attr, char *buf)
> {
> @@ -202,6 +216,7 @@ static const struct attribute *freq_attrs[] = {
> &dev_attr_act_freq.attr,
> &dev_attr_cur_freq.attr,
> &dev_attr_rp0_freq.attr,
> + &dev_attr_rpa_freq.attr,
> &dev_attr_rpe_freq.attr,
> &dev_attr_rpn_freq.attr,
> &dev_attr_min_freq.attr,
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
> index e8b9faeaef64..a6fdd2c062ff 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
> @@ -38,6 +38,7 @@
>
> #define FREQ_INFO_REC XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
> #define RPE_MASK REG_GENMASK(15, 8)
> +#define RPA_MASK REG_GENMASK(31, 16)
>
> #define GT_PERF_STATUS XE_REG(0x1381b4)
> #define CAGF_MASK REG_GENMASK(19, 11)
> @@ -328,6 +329,19 @@ static int pc_set_max_freq(struct xe_guc_pc *pc, u32 freq)
> freq);
> }
>
> +static void mtl_update_rpa_value(struct xe_guc_pc *pc)
> +{
> + struct xe_gt *gt = pc_to_gt(pc);
> + u32 reg;
> +
> + if (xe_gt_is_media_type(gt))
> + reg = xe_mmio_read32(>->mmio, MTL_MPA_FREQUENCY);
> + else
> + reg = xe_mmio_read32(>->mmio, MTL_GT_RPA_FREQUENCY);
> +
> + pc->rpa_freq = decode_freq(REG_FIELD_GET(MTL_RPA_MASK, reg));
> +}
> +
> static void mtl_update_rpe_value(struct xe_guc_pc *pc)
> {
> struct xe_gt *gt = pc_to_gt(pc);
> @@ -341,6 +355,25 @@ static void mtl_update_rpe_value(struct xe_guc_pc *pc)
> pc->rpe_freq = decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg));
> }
>
> +static void tgl_update_rpa_value(struct xe_guc_pc *pc)
> +{
> + struct xe_gt *gt = pc_to_gt(pc);
> + struct xe_device *xe = gt_to_xe(gt);
> + u32 reg;
> +
> + /*
> + * For PVC we still need to use fused RP1 as the approximation for RPe
> + * For other platforms than PVC we get the resolved RPe directly from
> + * PCODE at a different register
> + */
> + if (xe->info.platform == XE_PVC)
> + reg = xe_mmio_read32(>->mmio, PVC_RP_STATE_CAP);
> + else
> + reg = xe_mmio_read32(>->mmio, FREQ_INFO_REC);
> +
> + pc->rpa_freq = REG_FIELD_GET(RPA_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
> +}
> +
> static void tgl_update_rpe_value(struct xe_guc_pc *pc)
> {
> struct xe_gt *gt = pc_to_gt(pc);
> @@ -365,10 +398,13 @@ static void pc_update_rp_values(struct xe_guc_pc *pc)
> struct xe_gt *gt = pc_to_gt(pc);
> struct xe_device *xe = gt_to_xe(gt);
>
> - if (GRAPHICS_VERx100(xe) >= 1270)
> + if (GRAPHICS_VERx100(xe) >= 1270) {
> + mtl_update_rpa_value(pc);
> mtl_update_rpe_value(pc);
> - else
> + } else {
> + tgl_update_rpa_value(pc);
> tgl_update_rpe_value(pc);
> + }
>
> /*
> * RPe is decided at runtime by PCODE. In the rare case where that's
> @@ -447,6 +483,19 @@ u32 xe_guc_pc_get_rp0_freq(struct xe_guc_pc *pc)
> return pc->rp0_freq;
> }
>
> +/**
> + * xe_guc_pc_get_rpa_freq - Get the RPa freq
> + * @pc: The GuC PC
> + *
> + * Returns: RPa freq.
> + */
> +u32 xe_guc_pc_get_rpa_freq(struct xe_guc_pc *pc)
> +{
> + pc_update_rp_values(pc);
> +
> + return pc->rpa_freq;
> +}
> +
> /**
> * xe_guc_pc_get_rpe_freq - Get the RPe freq
> * @pc: The GuC PC
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.h b/drivers/gpu/drm/xe/xe_guc_pc.h
> index efda432fadfc..619f59cd633c 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.h
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.h
> @@ -21,6 +21,7 @@ int xe_guc_pc_unset_gucrc_mode(struct xe_guc_pc *pc);
> u32 xe_guc_pc_get_act_freq(struct xe_guc_pc *pc);
> int xe_guc_pc_get_cur_freq(struct xe_guc_pc *pc, u32 *freq);
> u32 xe_guc_pc_get_rp0_freq(struct xe_guc_pc *pc);
> +u32 xe_guc_pc_get_rpa_freq(struct xe_guc_pc *pc);
> u32 xe_guc_pc_get_rpe_freq(struct xe_guc_pc *pc);
> u32 xe_guc_pc_get_rpn_freq(struct xe_guc_pc *pc);
> int xe_guc_pc_get_min_freq(struct xe_guc_pc *pc, u32 *freq);
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc_types.h b/drivers/gpu/drm/xe/xe_guc_pc_types.h
> index 13810be015db..2978ac9a249b 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc_types.h
> +++ b/drivers/gpu/drm/xe/xe_guc_pc_types.h
> @@ -17,6 +17,8 @@ struct xe_guc_pc {
> struct xe_bo *bo;
> /** @rp0_freq: HW RP0 frequency - The Maximum one */
> u32 rp0_freq;
> + /** @rpa_freq: HW RPa frequency - The Achievable one */
> + u32 rpa_freq;
> /** @rpe_freq: HW RPe frequency - The Efficient one */
> u32 rpe_freq;
> /** @rpn_freq: HW RPN frequency - The Minimum one */
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